GS840E18AT-166 GSI TECHNOLOGY, GS840E18AT-166 Datasheet - Page 18

• Manufacturer Part Number: GS840E18AT-166
• Description: SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 8.5ns/3.5ns 100-Pin TQFP Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS840E18AT-166

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 4 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 3.3 V
• Number Of I/o Lines: 18 Bit
• Number Of Ports: 2
• Number Of Words: 256K

AC Test Conditions
Notes:
1.
2.
3.
4.
DC Electrical Characteristics
Rev: 1.12 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Input high level
Input low level
Input slew rate
Input reference level
Output reference level
Output load
Input Leakage Current
(except mode pins)
ZZ Input Current
Mode Pin Input Current
Output Leakage Current
Output High Voltage
Output High Voltage
Output Low Voltage
Include scope and jig capacitance.
Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted.
Output Load 2 for t
Device is deselected as defined by the Truth Table.
Parameter
Parameter
LZ
DQ
, t
HZ
, t
OLZ
and t
Output Load 1
OHZ
.
VT = 1.25 V
Symbol
Conditions
I
V
Fig. 1& 2
I
V
V
INZZ
I
INM
I
OL
1 V/ns
1.25 V
1.25 V
OH
OH
OL
IL
0.2 V
2.3 V
50Ω
* Distributed Test Jig Capacitance
18/31
30pF
*
I
I
OH
OH
= –4 mA, V
= –4 mA, V
Test Conditions
V
V
0V ≤ V
0V ≤ V
V
Output Disable,
V
DD
DD
OUT
GS840E18/32/36AT/B-190/180/166/150/100
IN
I
OL
≥ V
≥ V
= 0 to V
= 0 to V
= 4 mA
IN
IN
IN
IN
DDQ
DDQ
≤ V
≤ V
≥ V
≥ V
DD
= 2.375 V
= 3.135 V
DD
DQ
IH
IL
IH
IL
Output Load 2
5pF
*
2.5 V
225Ω
225Ω
–300 uA
–1 uA
–1 uA
–1 uA
–1 uA
–1uA
1.7 V
2.4 V
Min
© 1999, GSI Technology
300 uA
Max
0.4 V
1 uA
1 uA
1 uA
1 uA
1uA