GS8161Z36T-133 GSI Technology, GS8161Z36T-133 Datasheet

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GS8161Z36T-133

Manufacturer Part Number
GS8161Z36T-133
Description
8.5ns 133MHz 512K x 36 18MB pipelined and flow through synchronous NBT SRAM
Manufacturer
GSI Technology
Datasheet
100-Pin TQFP
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin-compatible with both pipelined and flow through
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
Functional Description
The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is an
18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like
ZBT, NtRAM, NoBL or other pipelined read/double late write
or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Rev: 2.15 11/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization
NtRAM™, NoBL™ and ZBT™ SRAMs
packages
Through
Pipeline
3-1-1-1
2-1-1-1
18Mb Pipelined and Flow Through
3.3 V
2.5 V
Flow
3.3 V
2.5 V
Synchronous NBT SRAM
Curr
Curr
Curr
Curr
Curr
Curr
Curr
Curr
tCycle
tCycle
t
t
KQ
KQ
(x32/x36)
(x32/x36)
(x32/x36)
(x32/x36)
(x18)
(x18)
(x18)
(x18)
Parameter Synopsis
1/36
-250 -225 -200 -166 -150 -133 Unit
280
330
275
320
175
200
175
200
2.5
4.0
5.5
5.5
255
300
250
295
165
190
165
190
2.7
4.4
6.0
6.0
GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D)
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) may
be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) is
implemented with GSI's high performance CMOS technology
and is available in JEDEC-standard 100-pin TQFP and
165-bump FP-BGA packages.
230
270
230
265
160
180
160
180
3.0
5.0
6.5
6.5
200
230
195
225
150
170
150
170
3.4
6.0
7.0
7.0
185
215
180
210
145
165
145
165
3.8
6.7
7.5
7.5
165
190
165
185
135
150
135
150
4.0
7.5
8.5
8.5
mA
mA
mA
mA
mA
mA
mA
mA
ns
ns
ns
ns
© 1998, GSI Technology
250 MHz–133 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS8161Z36T-133

GS8161Z36T-133 Summary of contents

Page 1

... Curr 175 165 160 150 145 (x18) Curr 200 190 180 170 165 (x32/x36) 1/36 250 MHz–133 MHz 3.3 V I/O 4.0 ns 7.5 ns 165 mA 190 mA 165 mA 185 mA 8.5 ns 8.5 ns 135 mA 150 mA 135 mA 150 mA © 1998, GSI Technology DD ...

Page 2

... DDQ DQP DDQ DDQ DDQ © 1998, GSI Technology ...

Page 3

... DQ D DQP Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) GS8161Z36T Pinout (Package T) 512K x 36 Top View 3/36 DQP ...

Page 4

... Scan Test Data Out Scan Test Clock Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low. Core power supply Ground Output driver power supply 4/36 ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 1998, GSI Technology ...

Page 5

... DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 1998, GSI Technology ...

Page 6

... DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 1998, GSI Technology ...

Page 7

... DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 1998, GSI Technology ...

Page 8

... GS8161Z18/32/36 NBT SRAM Functional Block Diagram Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Amps Sense Drivers Write 8/36 © 1998, GSI Technology ...

Page 9

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/ & determine which bytes will be written. All or none may be activated. A write cycle D 9/ and E ). Deassertion of any one of the Enable © 1998, GSI Technology ...

Page 10

... High-Z 1,2,3, High High High High High High © 1998, GSI Technology Notes 1,10 2 1,2,10 3 1,3, ...

Page 11

... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow Through Read/Write Control State Diagram 11/36 New Write Burst Write B D n+3 ƒ ƒ © 1998, GSI Technology ...

Page 12

... Transition and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 12/36 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 1998, GSI Technology ...

Page 13

... Pipeline and Flow through Read Write Control State Diagram 13/ Data Out W (Q Valid) D Notes: 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 1998, GSI Technology ...

Page 14

... H DD Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 14/ A[1:0] A[1:0] A[1:0] A[1: © 1998, GSI Technology BPR 1999.05.18 ...

Page 15

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH 15/36 2. The duration of SB tZZR on pipelined parts and V on flow DDQ SS © 1998, GSI Technology ...

Page 16

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 16/36 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 1998, GSI Technology Unit Notes ...

Page 17

... T 25 – not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 17/36 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 1998, GSI Technology ...

Page 18

... V DD 50% V Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 18/36 50% tKC Typ. Max. Unit 30pF © 1998, GSI Technology ...

Page 19

... OH3 OH DDQ 19/36 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 2.375 V 1 3.135 V 2.4 V — © 1998, GSI Technology Max — — 0.4 V ...

Page 20

... Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) 20/36 © 1998, GSI Technology ...

Page 21

... GSI Technology -133 Unit Min Max 7.5 ns — — 4.0 ns 1.5 — ns 1.5 — ns 1.5 ns — 0.5 — ns 8.5 ns — — 8.5 ns 3.0 ns — 3.0 — ns 1.5 — ns 0.5 — ...

Page 22

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Pipeline Mode Timing Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 22/36 Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 1998, GSI Technology ...

Page 23

... Flow Through Mode Timing Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 23/36 Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE . The JTAG output DD . TDO should be left unconnected. SS © 1998, GSI Technology tKQX D(G) ...

Page 24

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Description 24/36 © 1998, GSI Technology ...

Page 25

... Not Used Configuration 25/36 · · · TDO GSI Technology I/O JEDEC Vendor ID Code © 1998, GSI Technology ...

Page 26

... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 26/36 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 1998, GSI Technology ...

Page 27

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) 27/36 © 1998, GSI Technology ...

Page 28

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Description 28/36 Notes © 1998, GSI Technology ...

Page 29

... DD2 1 uA –300 –1 100 –1 1.7 — V 0.4 V — – 100 mV — V DDQ 100 mV V — JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 1998, GSI Technology ...

Page 30

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit 50 — ns — — ns — — ns — 30/36 tTKL tTKL © 1998, GSI Technology ...

Page 31

... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 31/ © 1998, GSI Technology ...

Page 32

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) BOTTOM Ø0. Ø0. Ø0.40~0. 1.0 10. 13±0.0 B 0.20(4 32/ 1.0 © 1998, GSI Technology ...

Page 33

... GS8161Z18T-150I GS8161Z18T-133I 512K x 36 GS8161Z36T-250I 512K x 36 GS8161Z36T-225I 512K x 36 GS8161Z36T-200I 512K x 36 GS8161Z36T-166I 512K x 36 GS8161Z36T-150I 512K x 36 GS8161Z36T-133I GS8161Z18D-250 GS8161Z18D-225 GS8161Z18D-200 GS8161Z18D-166 GS8161Z18D-150 GS8161Z18D-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816Z36-166IT. ...

Page 34

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 35

... Updated Pin Description table • Updated DQ on page 21 • Updated DQ on page 23 • Updated Operating Currrents table Content • Updated table on page 1; updated power numbers • Updated Recommended Operating Conditions table (added V references) DDQ 35/36 in pin description table. SS © 1998, GSI Technology ...

Page 36

... Updated Synchronous Truth Table Content/Format • Removed A and DQ numbers from pinouts • Updated timing diagrams • Added commercial “D” parts to ordering information table • Format updated • Updated format Content/Format • Updated timing diagrams • Updated mechanical drawings 36/36 © 1998, GSI Technology ...

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