GS8161Z18T-200 GSI Technology, GS8161Z18T-200 Datasheet
GS8161Z18T-200
Related parts for GS8161Z18T-200
GS8161Z18T-200 Summary of contents
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... Curr 175 165 160 150 145 (x18) Curr 200 190 180 170 165 (x32/x36) 1/36 250 MHz–133 MHz 3.3 V I/O 4.0 ns 7.5 ns 165 mA 190 mA 165 mA 185 mA 8.5 ns 8.5 ns 135 mA 150 mA 135 mA 150 mA © 1998, GSI Technology DD ...
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... Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) GS8161Z18T Pinout (Package Top View 2/ ...
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... DDQ DDQ DDQ DQP 51 A © 1998, GSI Technology ...
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... Scan Test Data Out Scan Test Clock Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low. Core power supply Ground Output driver power supply 4/36 ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 1998, GSI Technology ...
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... DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 1998, GSI Technology ...
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... DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 1998, GSI Technology ...
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... DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 1998, GSI Technology ...
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... GS8161Z18/32/36 NBT SRAM Functional Block Diagram Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Amps Sense Drivers Write 8/36 © 1998, GSI Technology ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/ & determine which bytes will be written. All or none may be activated. A write cycle D 9/ and E ). Deassertion of any one of the Enable © 1998, GSI Technology ...
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... High-Z 1,2,3, High High High High High High © 1998, GSI Technology Notes 1,10 2 1,2,10 3 1,3, ...
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... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow Through Read/Write Control State Diagram 11/36 New Write Burst Write B D n+3 ƒ ƒ © 1998, GSI Technology ...
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... Transition and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 12/36 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 1998, GSI Technology ...
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... Pipeline and Flow through Read Write Control State Diagram 13/ Data Out W (Q Valid) D Notes: 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 1998, GSI Technology ...
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... H DD Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 14/ A[1:0] A[1:0] A[1:0] A[1: © 1998, GSI Technology BPR 1999.05.18 ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH 15/36 2. The duration of SB tZZR on pipelined parts and V on flow DDQ SS © 1998, GSI Technology ...
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... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 16/36 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 1998, GSI Technology Unit Notes ...
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... T 25 – not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 17/36 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 1998, GSI Technology ...
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... V DD 50% V Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 18/36 50% tKC Typ. Max. Unit 30pF © 1998, GSI Technology ...
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... OH3 OH DDQ 19/36 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 2.375 V 1 3.135 V 2.4 V — © 1998, GSI Technology Max — — 0.4 V ...
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... Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) 20/36 © 1998, GSI Technology ...
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... GSI Technology -133 Unit Min Max 7.5 ns — — 4.0 ns 1.5 — ns 1.5 — ns 1.5 ns — 0.5 — ns 8.5 ns — — 8.5 ns 3.0 ns — 3.0 — ns 1.5 — ns 0.5 — ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Pipeline Mode Timing Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 22/36 Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 1998, GSI Technology ...
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... Flow Through Mode Timing Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 23/36 Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE . The JTAG output DD . TDO should be left unconnected. SS © 1998, GSI Technology tKQX D(G) ...
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... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Description 24/36 © 1998, GSI Technology ...
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... Not Used Configuration 25/36 · · · TDO GSI Technology I/O JEDEC Vendor ID Code © 1998, GSI Technology ...
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... JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 26/36 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 1998, GSI Technology ...
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... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) 27/36 © 1998, GSI Technology ...
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... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) Description 28/36 Notes © 1998, GSI Technology ...
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... DD2 1 uA –300 –1 100 –1 1.7 — V 0.4 V — – 100 mV — V DDQ 100 mV V — JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 1998, GSI Technology ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit 50 — ns — — ns — — ns — 30/36 tTKL tTKL © 1998, GSI Technology ...
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... All dimensions are in millimeters (mm). 2. Package width and length do not include mold protrusion. Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) θ 0.10 0.15 1.40 1.45 0.30 0.40 0.20 — e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 31/ © 1998, GSI Technology ...
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... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18(T/D)/GS8161Z32(D)/GS8161Z36(T/D) BOTTOM Ø0. Ø0. Ø0.40~0. 1.0 10. 13±0.0 B 0.20(4 32/ 1.0 © 1998, GSI Technology ...
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... GS8161Z36T-225 512K x 36 GS8161Z36T-200 512K x 36 GS8161Z36T-166 512K x 36 GS8161Z36T-150 512K x 36 GS8161Z36T-133 GS8161Z18T-250I GS8161Z18T-225I GS8161Z18T-200I GS8161Z18T-166I GS8161Z18T-150I GS8161Z18T-133I 512K x 36 GS8161Z36T-250I 512K x 36 GS8161Z36T-225I 512K x 36 GS8161Z36T-200I 512K x 36 GS8161Z36T-166I 512K x 36 ...
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... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 2.15 11/2004 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...
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... Updated Pin Description table • Updated DQ on page 21 • Updated DQ on page 23 • Updated Operating Currrents table Content • Updated table on page 1; updated power numbers • Updated Recommended Operating Conditions table (added V references) DDQ 35/36 in pin description table. SS © 1998, GSI Technology ...
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... Updated Synchronous Truth Table Content/Format • Removed A and DQ numbers from pinouts • Updated timing diagrams • Added commercial “D” parts to ordering information table • Format updated • Updated format Content/Format • Updated timing diagrams • Updated mechanical drawings 36/36 © 1998, GSI Technology ...