GS832132E-133 GSI TECHNOLOGY, GS832132E-133 Datasheet - Page 25

• Manufacturer Part Number: GS832132E-133
• Description: SRAM Chip Sync Quad 2.5V/3.3V 32M-Bit 1M x 32 8.5ns/4ns 165-Pin FBGA Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS832132E-133

• Package: 165FBGA
• Timing Type: Synchronous
• Density: 32 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 2.5|3.3 V
• Address Bus Width: 20 Bit
• Number Of I/o Lines: 32 Bit
• Number Of Ports: 4
• Number Of Words: 1M

JTAG TAP Instruction Set Summary
Rev: 1.05 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Notes:
1.
2.
Instruction
SAMPLE-Z
PRELOAD
Instruction codes expressed in binary, MSB on left, LSB on right.
Default instruction automatically loaded at power-up and in test-logic-reset state.
SAMPLE/
EXTEST
IDCODE
BYPASS
RFU
RFU
GSI
Code
000
001
010
011
100
101
110
111
Places the Boundary Scan Register between TDI and TDO.
Preloads ID Register and places it between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
Forces all RAM output drivers to High-Z.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Captures I/O ring contents. Places the Boundary Scan Register between TDI and
TDO.
GSI private instruction.
Do not use this instruction; Reserved for Future Use.
Replicates BYPASS instruction. Places Bypass Register between TDI and TDO.
Places Bypass Register between TDI and TDO.
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Description
GS832118/32/36E-250/225/200/166/150/133
© 2003, GSI Technology
Notes
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