GS832132E-133 GSI TECHNOLOGY, GS832132E-133 Datasheet - Page 23

• Manufacturer Part Number: GS832132E-133
• Description: SRAM Chip Sync Quad 2.5V/3.3V 32M-Bit 1M x 32 8.5ns/4ns 165-Pin FBGA Tray
• Manufacturer: GSI TECHNOLOGY

Specifications of GS832132E-133

• Package: 165FBGA
• Timing Type: Synchronous
• Density: 32 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 2.5|3.3 V
• Address Bus Width: 20 Bit
• Number Of I/o Lines: 32 Bit
• Number Of Ports: 4
• Number Of Words: 1M

Tap Controller Instruction Set
Overview
There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific
(Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be
implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load
address, data or control signals into the RAM or to preload the I/O buffers.
When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01.
When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired
instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the
TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this
device is listed in the following table.
Instruction Descriptions
BYPASS
Rev: 1.05 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This
occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-
tate testing of other devices in the scan path.
1
0
Test Logic Reset
Run Test Idle
0
1
JTAG Tap Controller State Diagram
1
1
23/32
Capture DR
1
Update DR
Pause DR
Select DR
Exit1 DR
Shift DR
Exit2 DR
0
0
1
1
0
1
0
GS832118/32/36E-250/225/200/166/150/133
1
0
0
0
1
1
Capture IR
1
Update IR
Pause IR
Select IR
Exit1 IR
Exit2 IR
Shift IR
0
1
1
0
1
0
0
© 2003, GSI Technology
1
0
0
0