GS832132E-133 GSI TECHNOLOGY, GS832132E-133 Datasheet

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GS832132E-133

Manufacturer Part Number
GS832132E-133
Description
SRAM Chip Sync Quad 2.5V/3.3V 32M-Bit 1M x 32 8.5ns/4ns 165-Pin FBGA Tray
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS832132E-133

Package
165FBGA
Timing Type
Synchronous
Density
32 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
2.5|3.3 V
Address Bus Width
20 Bit
Number Of I/o Lines
32 Bit
Number Of Ports
4
Number Of Words
1M
165-Bump FP-BGA
Commercial Temp
Industrial Temp
Features
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• LBO pin for Linear or Interleaved Burst mode
• Internal input resistors on mode pins allow floating mode pins
• Byte Write (BW) and/or Global Write (GW) operation
• Internal self-timed write cycle
• Automatic power-down for portable applications
• JEDEC-standard 165-bump FP-BGA package
• RoHS-compliant 165-bump BGA package available
Functional Description
Applications
The GS832118/32/36E is a 37,748,736-bit high performance
synchronous SRAM with a 2-bit burst address counter.
Although of a type originally developed for Level 2 Cache
applications supporting high performance CPUs, the device
now finds application in synchronous SRAM applications,
ranging from DSP main store to networking chip set support.
Controls
Addresses, data I/Os, chip enable (E1), address burst control
inputs (ADSP, ADSC, ADV) and write control inputs (Bx,
BW, GW) are synchronous and are controlled by a positive-
edge-triggered clock input (CK). Output enable (G) and power
down control (ZZ) are asynchronous inputs. Burst cycles can
be initiated with either ADSP or ADSC inputs. In Burst mode,
subsequent burst addresses are generated internally and are
controlled by ADV. The burst address counter may be
configured to count in either linear or interleave order with the
Linear Burst Order (LBO) input. The Burst function need not
be used. New addresses can be loaded on every cycle with no
degradation of chip performance.
Rev: 1.05 12/2007
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Through
Pipeline
3-1-1-1
2-1-1-1
Flow
2M x 18, 1M x 32, 1M x 36
36Mb Sync Burst SRAMs
Curr
Curr
Curr
Curr
tCycle
tCycle
t
t
(x32/x36)
(x32/x36)
KQ
KQ
(x18)
(x18)
Parameter Synopsis
1/32
-250 -225 -200 -166 -150 -133 Unit
285
350
205
235
2.5
4.0
6.5
6.5
265
320
195
225
2.7
4.4
7.0
7.0
Flow Through/Pipeline Reads
The function of the Data Output register can be controlled by
the user via the FT mode pin (Pin 14). Holding the FT mode
pin low places the RAM in Flow Through mode, causing
output data to bypass the Data Output Register. Holding FT
high places the RAM in Pipeline mode, activating the rising-
edge-triggered Data Output Register.
SCD Pipelined Reads
The GS832118/32/36E is a SCD (Single Cycle Deselect)
pipelined synchronous SRAM. DCD (Dual Cycle Deselect)
versions are also available. SCD SRAMs pipeline deselect
commands one stage less than read commands. SCD RAMs
begin turning off their outputs immediately after the deselect
command has been captured in the input registers.
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable
(BW) input combined with one or more individual byte write
signals (Bx). In addition, Global Write (GW) is available for
writing all bytes at one time, regardless of the Byte Write
control inputs.
Sleep Mode
Low power (Sleep mode) is attained through the assertion
(High) of the ZZ signal, or by stopping the clock (CK).
Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS832118/32/36E operates on a 2.5 V or 3.3 V power
supply. All input are 3.3 V and 2.5 V compatible. Separate
output power (V
from the internal circuits and are 3.3 V and 2.5 V compatible.
245
295
185
210
3.0
5.0
7.5
7.5
GS832118/32/36E-250/225/200/166/150/133
220
260
175
200
3.5
6.0
8.0
8.0
210
240
165
190
3.8
6.6
8.5
8.5
DDQ
185
215
155
175
4.0
7.5
8.5
8.5
) pins are used to decouple output noise
mA
mA
mA
mA
ns
ns
ns
ns
© 2003, GSI Technology
250 MHz–133 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS832132E-133

GS832132E-133 Summary of contents

Page 1

... Curr 205 195 185 175 165 (x18) Curr 235 225 210 200 190 (x32/x36) 1/32 250 MHz–133 MHz 3.3 V I/O ) pins are used to decouple output noise DDQ 4.0 ns 7.5 ns 185 mA 215 mA 8.5 ns 8.5 ns 155 mA 175 mA © 2003, GSI Technology DD ...

Page 2

... E3 BW ADSC TDI A1 TDO A A TMS A0 TCK A 2/ ADV ADSP DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2003, GSI Technology ...

Page 3

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 ADSC TDI A1 TDO A A TMS A0 TCK A 3/ ADV ADSP DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 2003, GSI Technology ...

Page 4

... TDI A1 TDO A A TMS A0 TCK A 4/ ADV ADSP DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2003, GSI Technology ...

Page 5

... Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect Low Core power supply I/O and Core Ground Output driver power supply 5/32 I/Os; active low D © 2003, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 GS832118/32/36 Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/32 A Memory Array Parity Encode Parity Compare 36 – DQx1 DQx9 NC © 2003, GSI Technology ...

Page 7

... Interleaved Burst L Flow Through Pipeline Active ZZ Standby nterleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 7/ A[1:0] A[1:0] A[1:0] A[1: © 2003, GSI Technology BPR 1999.05.18 ...

Page 8

... C D Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 may be used in any combination with BW to write single or multiple bytes Notes and/ © 2003, GSI Technology ...

Page 9

... Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 State Diagram ADSP ADSC Key 9/32 ADV High High High High High © 2003, GSI Technology ...

Page 10

... ADSP is tied high and ADV is tied low. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 Simplified State Diagram X Deselect First Write Burst Write CR CW 10/ First Read Burst Read BW, and GW) control inputs, and © 2003, GSI Technology ...

Page 11

... Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 Simplified State Diagram with G X Deselect First Write Burst Write 11/ First Read Burst Read CR © 2003, GSI Technology ...

Page 12

... Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2003, GSI Technology Unit Notes ...

Page 13

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 13/32 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2003, GSI Technology ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ V /2 DDQ Fig. 1 Output Load 1 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance 14/32 20% tKC DD IL Typ. Max. Unit © 2003, GSI Technology ...

Page 15

... OUT I Output Disable OUT –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 15/32 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – – 2.375 V 1 3.135 V 2.4 V — © 2003, GSI Technology Max — — 0.4 V ...

Page 16

... Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 16/32 © 2003, GSI Technology ...

Page 17

... GSI Technology -133 Unit Min Max 7.5 — ns — 4.0 ns 1.5 — ns 1.5 ns — 1.5 ns — 0.5 ns — 8.5 ns — 8.5 ns — ...

Page 18

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 18/32 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2003, GSI Technology Deselect tKQX tHZ ...

Page 19

... Flow Through Mode Timing Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 19/32 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2003, GSI Technology tKQX ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 Sleep Mode Timing Diagram tKH tKH tKC tKC tKL tKL tZZS tZZH 20/32 2. The duration of SB tZZR . The JTAG output DD . TDO should be left unconnected. SS © 2003, GSI Technology ...

Page 21

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 Description 21/32 © 2003, GSI Technology ...

Page 22

... Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller Not Used Configuration 22/32 · · · TDO GSI Technology I/O JEDEC Vendor ID Code © 2003, GSI Technology ...

Page 23

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 23/32 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2003, GSI Technology ...

Page 24

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 24/32 © 2003, GSI Technology ...

Page 25

... Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 Description 25/32 Notes © 2003, GSI Technology ...

Page 26

... DD3 0.8 V –0.3 0 +0.3 V DD2 DD2 0 –0.3 DD2 –300 1 uA 100 uA –1 – 1.7 V — 0.4 V — – 100 mV — V DDQ 100 mV V — JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2003, GSI Technology ...

Page 27

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — — — — ns 27/32 tTKL tTKL © 2003, GSI Technology ...

Page 28

... Package Dimensions—165-Bump FPBGA (Package E) A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS832118/32/36E-250/225/200/166/150/133 BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 15±0.05 B 0.20(4x) 28/32 A1 CORNER 1.0 © 2003, GSI Technology ...

Page 29

... Org Part Number GS832118E-250 GS832118E-225 GS832118E-200 GS832118E-166 GS832118E-150 GS832118E-133 GS832132E-250 GS832132E-225 GS832132E-200 GS832132E-166 GS832132E-150 GS832132E-133 GS832136E-250 GS832136E-225 GS832136E-200 GS832136E-166 GS832136E-150 GS832136E-133 GS832118E-250I GS832118E-225I GS832118E-200I GS832118E-166I GS832118E-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832118E-166IT. ...

Page 30

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS832118E-133I GS832132E-250I GS832132E-225I GS832132E-200I GS832132E-166I GS832132E-150I GS832132E-133I GS832136E-250I GS832136E-225I GS832136E-200I GS832136E-166I GS832136E-150I GS832136E-133I GS832118GE-250 GS832118GE-225 GS832118GE-200 GS832118GE-166 GS832118GE-150 GS832118GE-133 GS832132GE-250 GS832132GE-225 GS832132GE-200 GS832132GE-166 GS832132GE-150 GS832132GE-133 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS832118E-166IT. ...

Page 31

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.05 12/2007 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 32

... Corrected “E” package mechanical drawing thickness to 1.4 mm • Updated format Format/Content • Added variation information to package mechanical • RoHS-compliant information added Content • Updated Truth Tables (pg Content • Removed Preliminary banner due to production status Content • Updated mechanical drawing 32/32 Page;Revisions;Reason © 2003, GSI Technology ...

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