ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet - Page 37

• Manufacturer Part Number: ZL50012QCG1
• Description: Switch Fabric 256 x 256 3.3V 160-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of ZL50012QCG1

• Package: 160LQFP
• Number Of Ports: 16
• Fabric Size: 256 x 256
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 3.3 V

15 - 13
12 - 9
8 - 7
6 - 0
15
External Read/Write Address: 001
0
Bit
External Read/Write Address: 010
Bit
Reset Value: 0000
Reset Value: 0000
0
15
0
14
0
BRCA6 - 0
BRSA3 - 0
14
0
Unused
MBPS
Name
Name
13
0
H
H
13
0
Table 16 - Internal Mode Selection (IMS) Register Bits (continued)
12
0
SA3
BR
12
Memory Block Programming Start: A zero to one transition of this bit starts the
memory block programming function. The MBPS, BPD0 to BPD2 bits in this register
must be defined in the same write operation. Once the MBPE bit in the control register
is set to high, the device requires 50 µs to complete the block programming. After the
programming function has finished, the MBPS bit returns to low indicating the opera-
tion is completed. When the MBPS is high, the MBPS or MBPE can be set to low to
abort the programming operation.
To ensure proper block programming operation, when MBPS is high the BPD0 to
BPD2 bits in this register must not be changed.
Whenever the microprocessor writes a one to the MBPS bit, the block programming
function is started, the user must maintain the same logical value to the other bits in
this register to avoid any change in the device setting.
Reserved. In normal functional mode, these bits MUST be set to zero.
BER Receive Stream Address Bits: The binary value of these bits refers to the input
stream which receives the BER data.
BER Receive Channel Address Bits: The binary value of these bits refers to the
input channel in which the BER data starts to be compared.
CKINP
Table 17 - BER Start Receiving Register (BSRR) Bits
11
H
H
SA2
BR
11
FPINP
10
SA1
BR
10
CK2P
9
SA0
BR
Zarlink Semiconductor Inc.
9
ZL50012
FP2P
8
8
0
40
CK1P
7
7
0
Description
Description
FP1P
CA6
BR
6
6
CA5
CK0P
BR
5
5
CA4
BR
FP0P
4
4
CA3
BR
3
BPD
3
2
CA2
BR
2
BPD
2
1
CA1
BR
1
BPD
Data Sheet
1
0
CA0
BR
0
MBPS
0