ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet - Page 28

• Manufacturer Part Number: ZL50012QCG1
• Description: Switch Fabric 256 x 256 3.3V 160-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of ZL50012QCG1

• Package: 160LQFP
• Number Of Ports: 16
• Fabric Size: 256 x 256
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 3.3 V

2.6
The ZL50012 has one on-chip BER transmitter and one BER receiver. The transmitter can transmit onto a single
STo output stream only. The transmitter provides a BER sequence (2
from any channel in the frame and lasts from one channel up to one frame time (125 µs). The transmitter output
channel(s) are specified by programming the connection memory location(s) corresponding to the channel(s) of the
selected output stream: Bit 0 to 2 of the connection memory location(s) should be programmed to the BER test
mode (see Table 30 on page 53).
Multiple connection memory locations can be programmed for BER test such that the BER patterns can be
transmitted for several output channels which are consecutive. If the transmitting output channels are not
consecutive, the BER receiver will not compare the bit patterns correctly.
The number of output channels which the BER transmitter occupies also has to be the same as the number of
channels defined in the BER Length Register. The BER Length Register defines how many BER channels to be
monitored by the BER receiver.
Registers used for setting up the BER test are as follows:
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•
•
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As described above, the SBER bit in the control register controls the BER transmitter and receiver. To carry out the
BER test, users should set the SBER bit to zero to disable the BER transmitter during the programming of the
connection memory for the BER test. When the BER transmitter is disabled, the transmitter output is all ones.
Hence any output channel whose connection memory has been programmed to BER test mode will also output all
ones. Upon the completion of programming the connection memory for the BER test, set the SBER bit to one to
start the BER transmitter and receiver for the BER testing. They must be allowed to run for several frames (2
frames plus the network delay between STo and STi) before the BER receiver can correctly identify errors in the
pattern. Thus after this time the bit error counter should be reset by using the CBER bit in the Control Register - set
CBER to one then back to zero. From now on, the count will be the actual number of errors which occurred during
the test. The count will stop at FFFF and the counter will not increment even if more errors occurred.
Control Register (CR) - The CBER bit is used to clear the bit error counter and the BER Count Register
(BCR). The SBER bit is used to start or stop the BER transmitter and BER receiver.
BER Start Receiving Register (BSRR) - Defines the input stream and channel from where the BER
sequence will start to be compared.
BER Length Register (BLR) - Defines how many channels the sequence will last.
BER Count Register (BCR) - Contains the number of counted errors. When the error count reaches Hex
FFFF, the bit error counter will stop so that it will not overflow. Consequently the BER Count Register will
also stop at FFFF. The CBER bit in the Control Register is used to reset the bit error counter and the BER
Count Register.
Bit Error Rate (BER) Test
Zarlink Semiconductor Inc.
ZL50012
31
15
-1 Pseudo Random Code) which can start
Data Sheet