ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet - Page 15

• Manufacturer Part Number: ZL50012QCG1
• Description: Switch Fabric 256 x 256 3.3V 160-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of ZL50012QCG1

• Package: 160LQFP
• Number Of Ports: 16
• Fabric Size: 256 x 256
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 3.3 V

2.1.3
When the negative input frame pulse and negative input clock formats are used, the input frame boundary is
defined by the falling edge of the CKi input clock while the FPi is low. When the input data rate is 2.048 Mb/s,
4.096 Mb/s or 8.192 Mb/s, there are 32, 64 or 128 channels per every ST-BUS frame respectively. Figure 7 shows
the details:
2.1.4
The ZL50012 has a Frame Boundary Determinator (FBD) allowing substantial increase of the CKi input clock jitter
tolerance. The FBD circuit is enabled by setting the Control Register bits FBDEN and FBDMODE to HIGH. By
default the FBD is disabled. Both the FBDEN and FBDMODE bits should be set HIGH during normal operation. The
device can have 20 ns of input clock jitter tolerance (on CKi and FPi) when the FBD is fully enabled.
(16.384MHz)
Input Frame Boundary
(2.048Mb/s)
(4.096Mb/s)
(8.192Mb/s)
ST-BUS Input Timing
(4.096MHz)
(8.192MHz)
Improved Input Jitter Tolerance with Frame Boundary Determinator
(8kHz)
CKi
CKi
CKi
FPi
FPi
FPi
STi
STi
STi
3
1
2
0
1 0
Figure 7 - ST-BUS Input Timing for Various Input Data Rates
0
7
7
6
7
5
Channel 0
6
4
3
5
2
6
Channel 0
1 0
4
7
Zarlink Semiconductor Inc.
3
6
5
Channel 1
5
Channel 0
ZL50012
2
4
3
1
18
2
4
1 0
0
6
3
Channel 126
5
6
4
Channel 31
3
5
2
Input Frame Boundary
2
Channel 63
1 0
4
7
3
6
1
5
Channel 127
2
4
3
1
2
0
1 0
0
Data Sheet
7 6
7
7