ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet - Page 25

• Manufacturer Part Number: ZL50012QCG1
• Description: Switch Fabric 256 x 256 3.3V 160-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of ZL50012QCG1

• Package: 160LQFP
• Number Of Ports: 16
• Fabric Size: 256 x 256
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 3.3 V

By default, when the input channel delay and output channel delay are set to zero, the data throughput delay (T) is:
T = 2 frames + (m-n). Figure 21 shows the throughput delay when the input Ch0 is switched to the output Ch0.
When the input channel delay is enabled and the output channel delay is disabled, the data throughput delay is: T =
3 frames - α + (m-n). Figure 22 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
When the input channel delay is disabled and the output channel delay is enabled, the throughput delay is: T = 2
frames + β + (m-n). Figure 23 shows the data throughput delay when the input Ch0 is switched to the output Ch0.
Serial Output Data
Serial Output Data
Serial Output Data
Serial Output Data
Serial Input Data
Serial Input Data
Serial Input Data
Figure 21 - Data Throughput Delay when input and output channel delay are disabled for Input
Figure 23 - Data Throughput Delay when input channel delay is disabled and output channel
Figure 22 - Data Throughput Delay when input channel delay is enabled and output channel
(No Delay)
(No Delay)
Serial Input
(No Delay)
(No Delay)
Frame
Frame
(α = 1)
(α > 1)
Frame
(β = 1)
(β > 1)
Frame N-2 Data
Frame N
Frame N-1 Data
Frame N-3 Data
Frame N Data
Frame N
Frame N
Frame N Data
Frame N Data
Frame N-2 Data
Frame N-3 Data
delay is disabled for Input Ch0 switched to Output Ch0
delay is enabled for Input Ch0 switch to Output Ch0
3 Frames - 1 channel + 0
Frame N-1 Data
Frame N+1Data
Input Channel Delay (from 1 to max# of channels, programmed by the STIN#CD6-0 bit)
Frame N+1
Frame N-2 Data
2 Frames + β + 0
Frame N+1 Data
Frame N Data
Frame N+1 Data
Frame N+1
Frame N+1
Frame N-1 Data
Frame N-2 Data
2 Frames + 0
Ch0 switched to Output Ch0
Zarlink Semiconductor Inc.
2 Frames + 1 + 0
Frame N+2 Data
ZL50012
Frame N+1 Data
Frame N+2
Frame N+2 Data
Frame N Data
Frame N-1 Data
Frame N+2 Data
Frame N+2
Frame N+2
Frame N-1 Data
Frame N Data
28
3 Frames - α + 0
Frame N+1 Data
Frame N+3 Data
Frame N+2 Data
Frame N+3
Frame N+3 Data
Frame N+3 Data
Frame N Data
Frame N+3
Frame N+3
Frame N+1 Data
Output Channel Delay: (from 1 to max# of channels,
programmed by the STO#CD6-0 bit)
Frame N Data
Frame N+4 Data
Frame N+2 Data
Frame N+3 Data
Frame N+1 Data
Frame N+4
Frame N+4 Data
Frame N+4 Data
Frame N+4
Frame N+4
Frame N+1 Data
Frame N+2 Data
Frame N+3 Data
Frame N+5 Data
Frame N+4 Data
Frame N+4 Data
Frame N+5
Frame N+2 Data
Frame N+5 Data
Frame N+5 Data
Frame N+5
Frame N+5
Frame N+3 Data
Frame N+2 Data
Data Sheet