ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet
ZL50012QCG1
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ZL50012QCG1 Summary of contents
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... Copyright 2002-2006, Zarlink Semiconductor Inc. All Rights Reserved. Flexible 512-ch Digital Switch Ordering Information ZL50012/QCC 160 Pin LQFP ZL50012/GDC 144 Ball LBGA ZL50012QCG1 160 Ball LQFP* Trays, Bake & Drypack ZL50012GDG2 144 Ball LBGA** Trays, Bake & Drypack *Pb Free Matte Tin **Pb Free Tin/Silver/Copper -40°C to +85°C • ...
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... The ZL50012 has features that are programmable on per-stream or per-channel basis including message mode, input bit delay, output bit advancement, constant throughput delay and high impedance output control. ZL50012 2 Zarlink Semiconductor Inc. Data Sheet ...
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... Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.0 JTAG Support 4.1 Test Access Port (TAP 4.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.3 Test Data Register 4.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 5.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.0 Detail Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ZL50012 Table of Contents 3 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 33 - ST-BUS Outputs (STo0 - 15) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 34 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Figure 35 - Output Driver Enable (ODE Figure 36 - Motorola Non-Multiplexed Bus Timing Figure 37 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 38 - Reset Pin Timing Diagram ZL50012 List of Figures 4 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 27 - Stream Output Offset Register (SOOR8 to SOOR15 Table 28 - Address Map for Memory Locations (512 x 512 DX, MSB of address = 1 Table 29 - Connection Memory Bit Assignment when the CMM bit = Table 30 - Connection Memory Bits Assignment when the CMM bit = ZL50012 List of Tables 5 Zarlink Semiconductor Inc. Data Sheet ...
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... ZL50012 • Added a new section to describe the improved input jitter tolerance with the frame boundary determinator. • Renamed bit 15 from Unused to FBDMODE and added description to clarify the frame boundary determinator operation. • Clarified FBDEN description. 9 Zarlink Semiconductor Inc. Data Sheet Change ...
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... VSS VDD 156 157 RESET 158 TDo 159 NC 160 NC Figure LQFP (JEDEC MS-026) Pinout Diagram ZL50012 160 Pin LQFP 0.5mm pin pitch JEDEC MS-026 (Top View) 10 Zarlink Semiconductor Inc. Data Sheet VDD 77 VSS 76 STOHZ 11 75 STOHZ 10 STOHZ STOHZ 8 STo11 72 71 ...
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... STo15 STOHZ D10 D11 15 13 STo12 STo13 D3 D15 D4 D7 D12 D14 STOHZ STOHZ D0 DTA D13 Zarlink Semiconductor Inc. Data Sheet CKi TDi TCK FPi TRST TMS TM2 TDo STi15 STi8 RESET STi14 STi9 STi13 STi12 STi7 STi10 STi11 STi6 STi5 STi4 DS ...
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... The clock falling edge defines the input frame boundary. The device also allows the clock rising edge to define the frame boundary by programming the CKINP bit in the Internal Mode Selection register. 12 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Mode Selection register. CKo1 ST-BUS Clock Output Tolerant Three-state Output): A 16.384 MHz or 8.192 MHz clock output. The clock falling edge defines the output frame boundary. The polarity of this signal can be changed using the Internal Mode Selection register. 13 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Output): This active low output indicates that a data bus transfer is complete. A pull-up resistor is required to hold this pin at HIGH level. CS Chip Select (5 V Tolerant Input): Active low input used by the microprocessor to enable the microprocessor port access. 14 Zarlink Semiconductor Inc. Data Sheet Description ...
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... Test Serial Data Out (3 V Tolerant Three-state Output): JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG is not enabled Connection Pins. These pins are not connected to the device internally. 15 Zarlink Semiconductor Inc. Data Sheet Description bus lines (D0-D15) during a ...
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... Mb/s, 4.096 Mb/s and/or 8.192 Mb/s). By using Zarlink’s message mode capability, microprocessor data can be broadcast to the data output streams on a per channel basis. This feature is useful for transferring control and status information for external circuits or other ST-BUS devices ...
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... CKi (16.384MHz) CKINP = 0 CKi (16.384MHz) CKINP = 1 Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register ZL50012 Input Frame Boundary Input Frame Boundary Input Frame Boundary 17 Zarlink Semiconductor Inc. Data Sheet Input Frame Boundary Input Frame Boundary Input Frame Boundary ...
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... FBD is disabled. Both the FBDEN and FBDMODE bits should be set HIGH during normal operation. The device can have input clock jitter tolerance (on CKi and FPi) when the FBD is fully enabled. ZL50012 Channel Channel Channel Zarlink Semiconductor Inc. Data Sheet Channel Channel Channel 126 Channel 127 ...
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... Table 3 - FPo1 and CKo1 Output Programming CKFP2 0 1 Table 4 - FPo2 and CKo2 Output Programming ZL50012 FPo0 CKo0 Low Cycle 244 ns 4.096 MHz 122 ns 8.192 MHz FPo1 CKo1 61 ns 16.384 MHz 122 ns 8.192 MHz FPo2 CKo2 30 ns 32.768 MHz 61 ns 16.384 MHz 19 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz) CKOP = 1 Figure 9 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 1 FPo1 FP1P = 0 FPo1 FP1P = 1 CKo1 (16.384 MHz) CK1P = 0 CKo1 (16.384 MHz) CK1P = 1 Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 0 ZL50012 20 Zarlink Semiconductor Inc. Data Sheet ...
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... MHz) CK2P = 1 Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 0 FPo2 FP2P = 0 FPo2 FP2P = 1 CKo2 (16.384 MHz) CK2P = 0 CKo2 (16.384 MHz) CK2P = 1 Figure 13 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 1 ZL50012 21 Zarlink Semiconductor Inc. Data Sheet ...
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... STo 0 7 (2.048 Mb/s) STo (4.096 Mb/s) Channel 0 STo (8.192 Mb/s) Output Frame Boundary Figure 14 - ST-BUS Output Timing for Various Output Data Rates ZL50012 Channel Channel Channel Zarlink Semiconductor Inc. Data Sheet Channel Channel Channel 126 Channel 127 Output Frame Boundary ...
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... Figure 16. The input delay is enabled by Bit the Stream Input Delay Registers (SIDR). The input bit delay can vary from bits. ZL50012 Delay = 2 Last Channel Ch0 Zarlink Semiconductor Inc. Data Sheet Last Channel -1 Last Channel Last Channel -2 Last Channel - Last Channel - ...
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... Output Frame Boundary Figure 17 - Output Channel Delay Timing Diagram ZL50012 Ch0 Bit Delay = 1 Ch0 Figure 16 - Input Bit Delay Timing Diagram Last Channel - Last Channel - Delay = 2 Ch0 Last Channel Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Last Channel Last Channel - Last Channel - ...
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... Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively Figure 19 - Fractional Output Bit Advancement Timing Diagram ZL50012 Ch0 Bit Delay = 1 Ch0 Last Channel Bit 1 Bit 0 Last Channel Bit 7 Bit 0 Output Frame Boundary 25 Zarlink Semiconductor Inc. Data Sheet Ch1 Ch1 Ch0 Bit 7 Bit 6 Ch0 Bit 6 ...
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... Note: Last Channel = 31, 63, 127 for 2.048 Mb/s, 4.096 Mb/s and 8.192 Mb/s mode respectively Figure 20 - Example: External High Impedance Control Timing ZL50012 HiZ Ch1 Ch2 Ch3 STOHZ Advancement (Programmable in 4 steps of 15 1/4 bit) 26 Zarlink Semiconductor Inc. Data Sheet Last Ch -2 Ch0 Last Ch-1 Last Ch ...
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... Output Channel Possible Output channel Number ( 127 Input Channel Delay OFF Output Channel Delay frames + β + (n-m) Table 7 - Data Throughput Delay 27 Zarlink Semiconductor Inc. Data Sheet 127 delay (β 127 Input Channel Delay ON Output Channel Delay frames - α + β + (n-m) ...
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... Output Channel Delay: (from 1 to max# of channels, programmed by the STO#CD6-0 bit) 2 Frames + β Frame N-2 Data Frame N-1 Data Frame N Data 28 Zarlink Semiconductor Inc. Data Sheet Frame N+4 Frame N+5 Frame N+4 Data Frame N+5 Data Frame N+2 Data Frame N+3 Data ...
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... STO#CD6-0 bit) 3 Frames - α + β Frames - 1 + β Frame N-3 Data Frame N-2 Data Frame N-1 Data Ch0 switched to Output Ch0 29 Zarlink Semiconductor Inc. Data Sheet Frame N+4 Frame N+5 Frame N+4 Data Frame N+5 Data Frame N+3 Data Frame N+4 Data ...
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... MBPS bit or the MBPE bit to low. If the MBPE bit is used to terminate the block programming before completion, users have to set the MBPS bit from high to low before enabling other device operation Table 8 - Connection Memory in Block Programming Mode ZL50012 Zarlink Semiconductor Inc. Data Sheet BPD2 BPD1 BPD0 ...
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... CBER to one then back to zero. From now on, the count will be the actual number of errors which occurred during the test. The count will stop at FFFF and the counter will not increment even if more errors occurred. ZL50012 15 -1 Pseudo Random Code) which can start 31 Zarlink Semiconductor Inc. Data Sheet ...
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... No bit replacement occurs in Quadrant 2 Table 12 - Quadrant Frame 2 LSB Replacement STIN#QEN3 1 Replace LSB of every channel in Quadrant 3 with "1" bit replacement occurs in Quadrant 3 Table 13 - Quadrant Frame 3 LSB Replacement ZL50012 Quadrant 1 Quadrant Action Action Action Action 32 Zarlink Semiconductor Inc. Data Sheet Quadrant 127 ...
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... Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is internally pulled to Vdd when it is not driven from an external source. ZL50012 33 Zarlink Semiconductor Inc. Data Sheet ...
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... The Device Identification Register - The JTAG device ID for the ZL50012 is 0C35C14B Version<31:28>: 0000 Part No. <27:12>: 1100 0011 0101 1100 Manufacturer ID<11:1>: 0001 0100 101 LSB<0>: 1 4.4 BSDL A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the IEEE 1149 test interface. ZL50012 34 Zarlink Semiconductor Inc. Data Sheet . H ...
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... R/W Stream10 Input Delay Register, SIDR10 R/W Stream11 Input Control Register, SICR11 R/W Stream11 Input Delay Register, SIDR11 R/W Stream12 Input Control Register, SICR12 R/W Stream12 Input Delay Register, SIDR12 R/W Stream13 Input Control Register, SICR13 35 Zarlink Semiconductor Inc. Data Sheet ...
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... R/W Stream14 Output Control Register, SOCR14 H 21D R/W Stream14 Output Delay Register, SOOR14 H 21E R/W Stream15 Output Control Register, SOCR15 H 21F R/W Stream15 Output Delay Register, SOOR15 H Table 14 - Address Map for Device Specific Registers 36 Zarlink Semiconductor Inc. Data Sheet Register ...
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... CKIN CKFP CKFP CKFP CBER Description CKIN2 - 0 FPi Low Cycle 000 61 ns 001 122 ns 010 244 ns 011 - 111 Table 15 - Control Register (CR) Bits 37 Zarlink Semiconductor Inc. Data Sheet SBER MBPE OSB MS2 MS1 MS0 CKi 16.384 MHz 8.192 MHz 4.096 MHz Reserved ...
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... STo0-15 Pin Pin Bit HiZ HiZ HiZ Active MS2 - 0 Memory Selection 000 Connection Memory Read/Write 001 Data memory Read 010 - 111 Reserved 38 Zarlink Semiconductor Inc. Data Sheet MBPE OSB MS2 MS1 MS0 STOHZ 0-15 Driven High Driven High Driven High Active ...
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... BPD0 to BPD2 are loaded into Bit 0 to Bit 2 of the connection memory. Bit 3 to Bit 11 of the connection memory are zeroed. Table 16 - Internal Mode Selection (IMS) Register Bits ZL50012 CK2P FP2P CK1P FP1P CK0P FP0P Description 39 Zarlink Semiconductor Inc. Data Sheet BPD BPD BPD MBPS ...
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... BER data starts to be compared. Table 17 - BER Start Receiving Register (BSRR) Bits ZL50012 CK2P FP2P CK1P FP1P CK0P Description SA1 SA0 CA6 CA5 Description 40 Zarlink Semiconductor Inc. Data Sheet FP0P BPD BPD BPD MBPS CA4 CA3 CA2 CA1 CA0 ...
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... BER Count Bits: The binary value of these bits refers to the bit error counts. When it reaches its maximum value of Hex FFFF, the value will not be changed any more Table 19 - BER Count Register (BCR) Bits ZL50012 BL7 BL6 BL5 Description Description 41 Zarlink Semiconductor Inc. Data Sheet BL4 BL3 BL2 BL1 BL0 ...
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... STIN5 STIN5 QEN3 QEN2 QEN1 0 0 STIN6 STIN6 STIN6 QEN3 QEN2 QEN1 0 0 STIN7 STIN7 STIN7 QEN3 QEN2 QEN1 Description 42 Zarlink Semiconductor Inc. Data Sheet STIN0 STIN0 STIN0 STIN0 STIN0 STIN0 QEN0 SMP1 SMP0 DR2 DR1 DR0 STIN1 STIN1 STIN1 STIN1 ...
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... STIN7 QEN3 QEN2 QEN1 Description Sampling Point STIN#SMP1 STIN#DR2-0 000 Disabled - External pull-up or pull-down is required for ST-BUS input 001 010 011 100 - 111 43 Zarlink Semiconductor Inc. Data Sheet STIN0 STIN0 STIN0 STIN0 STIN0 STIN0 QEN0 SMP1 SMP0 DR2 DR1 DR0 STIN1 ...
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... STIN13 STIN13 QEN3 QEN2 QEN1 0 0 STIN14 STIN14 STIN14 QEN3 QEN2 QEN1 0 0 STIN15 STIN15 STIN15 QEN3 QEN2 QEN1 Description 44 Zarlink Semiconductor Inc. Data Sheet STIN8 STIN8 STIN8 STIN8 STIN8 STIN8 QEN0 SMP1 SMP0 DR2 DR1 DR0 STIN9 STIN9 STIN9 STIN9 ...
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... STIN15 QEN3 QEN2 QEN1 Description Sampling Point STIN#SMP1 STIN#DR2-0 000 Disabled - External pull-up or pull-down is required for ST-BUS input 001 010 011 100 - 111 45 Zarlink Semiconductor Inc. Data Sheet STIN8 STIN8 STIN8 STIN8 STIN8 STIN8 QEN0 SMP1 SMP0 DR2 DR1 DR0 STIN9 ...
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... STIN6 STIN6 STIN6 CD6 CD5 CD4 CD3 CD2 0 0 STIN7 STIN7 STIN7 STIN7 STIN7 CD6 CD5 CD4 CD3 CD2 Description 46 Zarlink Semiconductor Inc. Data Sheet STIN0 STIN0 STIN0 STIN0 STIN0 CD1 CD0 BD2 BD1 BD0 STIN1 STIN1 STIN1 STIN1 STIN1 CD1 ...
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... STIN14 STIN14 STIN14 STIN14 CD6 CD5 CD4 CD3 CD2 0 STIN15 STIN15 STIN15 STIN15 STIN15 CD6 CD5 CD4 CD3 CD2 Description 47 Zarlink Semiconductor Inc. Data Sheet STIN8 STIN8 STIN8B STIN8B STIN8B CD1 CD0 BD2 BD1 BD0 STIN9 STIN9 STIN9B STIN9B STIN9B CD1 ...
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... Reserved Output Data Rate STO#DR2-0 000 STOHZ driven high 001 010 011 100 - 111 48 Zarlink Semiconductor Inc. Data Sheet STOHZ0 STOHZ0 STOHZ0 STO0 STO0 STO0 DR2 DR1 DR0 STOHZ1 STOHZ1 ...
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... Reserved Output Data Rate STO#DR2-0 000 STOHZ driven high 001 010 011 100 - 111 49 Zarlink Semiconductor Inc. Data Sheet STOHZ8 STOHZ8 STO8 STO8 STO8 A1 A0 DR2 DR1 DR0 STOHZ9 STOHZ9 STO9 ...
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... CD4 CD3 CD2 CD1 STO7 STO7 STO7 STO7 STO7 STO7 CD6 CD5 CD4 CD3 CD2 CD1 Description Advanced By STO#FA1 Zarlink Semiconductor Inc. Data Sheet STO0 STO0 STO0 STO0 STO0 STO0 CD0 BD2 BD1 BD0 FA1 FA0 STO1 STO1 STO1 STO1 STO1 ...
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... CD3 CD2 CD1 CD0 STO15 STO1 STO15 STO15 STO15 STO15 CD5 CD4 CD3 CD2 CD1 CD0 Description Advanced By STO#FA1 Zarlink Semiconductor Inc. Data Sheet STO8B STO8 STO8 STO8 STO8 BD2 BD1 BD0 FA1 FA0 STO9 STO9 STO9 STO9 STO9 BD2 BD1 ...
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... Channels 0 to 127 are used when serial stream is at 8.192 Mb/s. Table 28 - Address Map for Memory Locations (512 x 512 DX, MSB of address = 1) ZL50012 A7 Stream # Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Stream Zarlink Semiconductor Inc. Data Sheet Channel Address (Ch 0-127 Channel # (Note (Note 126 127 (Note 4) ...
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... SSA0 SCA6 SCA5 SCA4 SCA3 Description MSG5 MSG4 MSG3 MSG2 MSG1 Description PCC PCC0 Output 0 0 Per Channel Tristate 0 1 Message Mode 1 0 BER Test Mode 1 1 Reserved 53 Zarlink Semiconductor Inc. Data Sheet SCA2 SCA1 SCA0 CMM = MSG0 PCC1 PCC0 CMM =1 ...
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... Sym. Min. Typ Max I 250 Zarlink Semiconductor Inc. Data Sheet Min. Max Units -0.5 5 -0.5 7 0.75 W ° +125 . ‡ Typ. Max Units °C 25 +85 3.3 3 5.5 V Units Test Conditions mA Output unloaded V V µA ≤ ...
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... CKIH t 63 CKIL rCKi fCKi Sym. Min FPIW t 110 FPIS t 120 FPIH t 220 CKIP t 110 CKIH t 110 CKIL rCKi fCKi 55 Zarlink Semiconductor Inc. Data Sheet Units Conditions ‡ Typ. Max. Units Notes 61 115 ‡ Typ. Max. Units Notes 122 220 122 ...
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... V and are for design aid only: not guaranteed and not subject to production testing. DD Input Frame Boundary N FPi CKi Figure 26 - Frame Boundary Timing with Input Clock (cycle-to-cycle) Variation ZL50012 t FPIW t FPH t CKIP t CKIL Sym. Min CKV t CKV t CKV 56 Zarlink Semiconductor Inc. Data Sheet t CKIH ‡ Typ Max. Units Notes 50 ns Input Frame Boundary ...
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... Input and Output Frame Offset ZL50012 Sym. Min. Typ FPV t FPV t FPV Sym. Min. Typ. Max. Units t FBOS Zarlink Semiconductor Inc. Data Sheet ‡ Max. Units Notes 50 ns Input Frame Boundary Notes Measured when there is no jitter on the CKi and FPi inputs. ...
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... MHz) Input Frame Boundary t FBOS FPo2 CKo2 (32.768 MHz) FPo2 or FPo1 CKo2 or FPo1 (16.384 MHz) FPo1 or FPo0 CKo1 or CKo0 (8.192 MHz) FPo0 CKo0 (4.096 MHz) Figure 28 - Input and Output Frame Boundary Offset ZL50012 Output Frame Boundary 58 Zarlink Semiconductor Inc. Data Sheet ...
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... FODR0 t 108 CKP0 t 54 CKH0 t 54 CKL0 rCK0 fCK0 t FPW0 t t FODF0 FODR0 t CKP0 t t CKH0 CKL0 t fCK0 59 Zarlink Semiconductor Inc. Data Sheet ‡ Typ. Max. Units Notes 244 270 ns C =30pF L 130 ns 130 ns 244 270 ns C =30pF L 130 ns 130 ‡ ...
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... FPW1 t 54 FODF1 t 54 FODR1 t 108 CKP1 t 54 CKH1 t 54 CKL1 rCK1 fCK1 t FPW1 t t FODF1 FODR1 t CKP1 t t CKH1 CKL1 t fCK1 60 Zarlink Semiconductor Inc. Data Sheet ‡ Typ. Max. Units Notes =30pF =30pF ‡ Typ. Max. Units Notes 122 140 ...
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... Min FPW2 t 20 FODF2 t 20 FODR2 t 47 CKP2 t 20 CKH2 t 20 CKL2 rCK2 fCK2 t FPW2 t t FODF2 FODR2 t CKP2 t t CKH2 CKL2 t fCK2 61 Zarlink Semiconductor Inc. Data Sheet ‡ Typ. Max. Units Notes =30pF =30pF ‡ Typ. Max. Units Notes =30pF ...
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... SIH2 Bit7 Ch0 t SIS4 t SIH4 Bit7 Bit6 Ch0 Ch0 t SIS8 t SIH8 Bit7 Bit6 Bit5 Bit4 Bit3 Ch0 Ch0 Ch0 Ch0 Ch0 62 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions Bit6 V TT Ch0 Bit5 Bit4 V TT Ch0 Ch0 V Bit2 Bit1 Bit0 V TT ...
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... SOD8 t SOD2 Bit7 Ch0 t SOD4 Bit7 Bit7 Ch0 Ch0 t SOD8 Bit7 Bit6 Bit5 Bit4 Bit3 Ch0 Ch0 Ch0 Ch0 Ch0 63 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions 30pF Bit7 V TT Ch0 Bit7 Bit7 V TT Ch0 Ch0 V Bit2 Bit1 Bit0 TT Ch0 ...
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... Valid Data Tri-state t ZD Tri-state Valid Data ODE t t ZD_ODE DZ_ODE STo Valid Data HiZ HiZ Figure 35 - Output Driver Enable (ODE) 64 Zarlink Semiconductor Inc. Data Sheet Test Max. Units Conditions =1K =30pF See Note ...
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... DHW t AKD 120/105 200/150 t 20 AKH , with timing corrected to cancel time taken to discharge DSD t CSS t RWS t ADS VALID ADDRESS VALID READ DATA t WDS VALID WRITE DATA t DDR t AKD 65 Zarlink Semiconductor Inc. Data Sheet 2 Units Test Conditions =30pF =30pF, R =1K (Note =30pF ...
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... TCKH t 80 TCKL t 10 TMSS t 10 TMSH t 20 TDIS t 60 TDIH t TDOD t 200 TRSTW t 1.0 RSTW t t TCKL TCKH t TCKP t TMSH t TDIH t TDOD t RSTW Figure 38 - Reset Pin Timing Diagram 66 Zarlink Semiconductor Inc. Data Sheet Typ. Max. Units Notes =30pF TRSTW ...
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... Zarlink Semiconductor 2002 All rights reserved. ISSUE ACN DATE APPRD. Package Code Previous package codes ...
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... Zarlink Semiconductor 2002 All rights reserved ISSUE 213834 ACN 213740 11Dec02 15Nov02 DATE APPRD. Package Code Previous package codes ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...