ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet - Page 30

• Manufacturer Part Number: ZL50012QCG1
• Description: Switch Fabric 256 x 256 3.3V 160-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of ZL50012QCG1

• Package: 160LQFP
• Number Of Ports: 16
• Fabric Size: 256 x 256
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 3.3 V

2.8
The device supports the non-multiplexed microprocessor. The microprocessor port consists of a 16-bit parallel data
bus (D0 to 15), a 12-bit address bus (A0 to 11) and four control signals (CS, DS, R/W and DTA). The parallel
microprocessor port provides fast access to the internal registers, the connection and the data memories.
The connection memory locations can be read or written via the 16-bit microprocessor port. On the other hand, the
data memory locations can only be read (but not written) from the microprocessor port.
For the connection memory write operation, D0 to 11 of the data bus will be used and D12 to 15 are ignored (D12 to
15 should be driven low). For the connection memory read operation, D0 to D11 will be used and D12 to D15 will
output zeros. For the data memory read operation, D0 to D7 will be used and D8 to D15 will output zeros.
See Table 28 on page 52 for the address mapping of the data memory. Refer to Figure 36 on page 65 for the
microprocessor port timing.
3.0
The RESET pin is used to reset the device. When the pin is low, it synchronously puts the device in its reset state.
It disables the STo0 - 15 outputs, drives the STOHZ 0 - 15 outputs to high, clears the device registers and the
internal counters.
Upon power up, the device should be initialized as follows:
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4.0
The ZL50012 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the
boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
4.1
The Test Access Port (TAP) accesses the ZL50012 test functions. It consists of three input pins and one output pin
as follows:
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Set ODE pin to low to disable the STo0-15 output and to drive the STOHZ 0-15 to high.
Set the TRST pin to low to disable the JTAG TAP controller.
Reset the device by pulsing the RESET pin to low for longer than 1ms.
After releasing the RESET pin from low to high, wait for 600 µs for the APLL module to be stabilized before
starting the first microprocessor port access cycle.
Program the register to define the frequency of the CKi input.
Wait for 600 µs for the APLL module to be stabilized before starting the next microprocessor port access
cycle.
Use the memory block programming mode to initialize the connection memory.
Release the ODE pin to high after the connection memory is programmed such that bus contention will not
occur at the serial stream outputs STo0-15.
Test Clock Input (TCK) - TCK provides the clock for the test logic. The TCK does not interfere with any on-
chip clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or
out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering
with the on-chip logic.
Test Mode Select Input (TMS) - The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven from an external source.
Microprocessor Port
Test Access Port (TAP)
Device Reset and Initialization
JTAG Support
Zarlink Semiconductor Inc.
ZL50012
33
Data Sheet