P89LV51RD2BBC NXP Semiconductors, P89LV51RD2BBC Datasheet - Page 8

• Manufacturer Part Number: P89LV51RD2BBC
• Description: MCU 8-Bit 89LV 80C51 CISC 64KB Flash 3.3V 44-Pin TQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89LV51RD2BBC

• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

NXP Semiconductors
Table 3.
P89LV51RB2_RC2_RD2_5
Product data sheet
Symbol
P2.7/A15
P3.0 to P3.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
P3.7/RD
PSEN
RST
EA
P89LV51RB2/RC2/RD2 pin description
Pin
TQFP44
25
5
7
8
9
10
11
12
13
26
4
29
PLCC44
31
11
13
14
15
16
17
18
19
32
10
35
Type
I/O
O
I/O with
internal
pull-up
I
I
O
O
I
I
I
I
I/O
I
I/O
I
O
O
O
O
I/O
I
I
Rev. 05 — 15 December 2009
…continued
Description
P2.7 — Port 2 bit 7.
A15 — Address bit 15.
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pull-ups. Port 3 pins are pulled HIGH by the internal pull-ups
when ‘1’s are written to them and can be used as inputs in this
state. As inputs, Port 3 pins that are externally pulled LOW will
source current (I
receives some control signals and a partial of high-order address
bits during the external host mode programming and verification.
P3.0 — Port 3 bit 0.
RXD — Serial input port.
P3.1 — Port 3 bit 1.
TXD — Serial output port.
P3.2 — Port 3 bit 2.
INT0 — External interrupt 0 input.
P3.3 — Port 3 bit 3.
INT1 — External interrupt 1 input.
P3.4 — Port 3 bit 4.
T0 — External count input to Timer/counter 0.
P3.5 — Port 3 bit 5.
T1 — External count input to Timer/counter 1.
P3.6 — Port 3 bit 6.
WR — External data memory write strobe.
P3.7 — Port 3 bit 7.
RD — External data memory read strobe.
Program Store Enable: PSEN is the read strobe for external
program memory. When the device is executing from internal
program memory, PSEN is inactive (HIGH). When the device is
executing code from external program memory, PSEN is
activated twice each machine cycle, except that two PSEN
activations are skipped during each access to external data
memory. A forced HIGH-to-LOW input transition on the PSEN pin
while the RST input is continually held HIGH for more than 10
machine cycles will cause the device to enter external host mode
programming.
Reset: While the oscillator is running, a HIGH logic state on this
pin for two machine cycles will reset the device. If the PSEN pin
is driven by a HIGH-to-LOW input transition while the RST input
pin is held HIGH, the device will enter the external host mode,
otherwise the device will enter the normal operation mode.
External Access Enable: EA must be connected to V
to enable the device to fetch code from the external program
memory. EA must be strapped to V
execution. The EA pin can tolerate a high voltage of 12 V.
P89LV51RB2/RC2/RD2
IL
) because of the internal pull-ups. Port 3 also
8-bit microcontrollers with 80C51 core
DD
for internal program
© NXP B.V. 2009. All rights reserved.
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