P89LV51RD2BBC NXP Semiconductors, P89LV51RD2BBC Datasheet - Page 27

• Manufacturer Part Number: P89LV51RD2BBC
• Description: MCU 8-Bit 89LV 80C51 CISC 64KB Flash 3.3V 44-Pin TQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89LV51RD2BBC

• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
6.4 Timers/counters 0 and 1
Table 13.
The two 16-bit Timer/counter registers: Timer 0 and Timer 1 can be configured to operate
either as timers or event counters (see
In the ‘Timer’ function, the register is incremented every machine cycle. Thus, one can
think of it as counting machine cycles. Since a machine cycle consists of six oscillator
periods, the count rate is
In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition at its
corresponding external input pin, T0 or T1. In this function, the external input is sampled
once every machine cycle.
When the samples show a HIGH in one cycle and a LOW in the next cycle, the count is
incremented. The new count value appears in the register in the machine cycle following
the one in which the transition was detected. Since it takes two machine cycles (12
oscillator periods) for 1-to-0 transition to be recognized, the maximum count rate is
the oscillator frequency. There are no restrictions on the duty cycle of the external input
signal, but to ensure that a given level is sampled at least once before it changes, it should
be held for at least one full machine cycle. In addition to the ‘Timer’ or ‘Counter’ selection,
Timer 0 and Timer 1 have four operating modes from which to select.
The ‘Timer’ or ‘Counter’ function is selected by control bits C/T in the special function
register TMOD. These two timer/counters have four operating modes, which are selected
by bit-pairs (M1, M0) in TMOD. Modes 0, 1, and 2 are the same for both timers/counters.
Mode 3 is different. The four operating modes are described in the following text.
Table 14.
Not bit addressable; reset value: 0000 0000B; reset source(s): any source.
IAP function
Read Security Bit, Double Clock,
SoftICE
Read Security Bit, Double Clock,
SoftICE
Erase sector
Bit
Symbol
IAP function calls
TMOD - Timer/counter mode control register (address 89H) bit allocation
T1GATE
7
Rev. 05 — 15 December 2009
T1C/T
6
1
6
of the oscillator frequency.
…continued
T1M1
IAP call parameters
Input parameters:
ACC = 07H
Return parameter(s):
ACC = 000 S/N-match 0 SB 0 DBL_CLK
Input parameters:
ACC = 07H
Return parameter(s):
ACC = 00 SoftICE S/N-match 0 SB 0 DBL_CLK
Input parameters:
R1 = 08H
DPH = sector address high byte
DPL = sector address low byte
Return parameter(s):
ACC = 00 = pass
ACC = !00 = fail
5
Table 14
P89LV51RB2/RC2/RD2
T1M0
4
and
8-bit microcontrollers with 80C51 core
T0GATE
Table
3
15).
T0C/T
2
© NXP B.V. 2009. All rights reserved.
T0M1
1
T0M0
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1
0
12
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