P89LV51RD2BBC NXP Semiconductors, P89LV51RD2BBC Datasheet - Page 44

• Manufacturer Part Number: P89LV51RD2BBC
• Description: MCU 8-Bit 89LV 80C51 CISC 64KB Flash 3.3V 44-Pin TQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89LV51RD2BBC

• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
Fig 17. SPI transfer format with CPHA = 0
SPICLK (CPOL = 0)
SPICLK (CPOL = 1)
SPICLK cycle #
(for reference)
(from master)
SS (to slave)
Table 29.
Table 30.
Table 31.
Bit addressable; reset source(s): any reset; reset value: 0000 0000B.
Table 32.
(from slave)
Bit
2
1
0
PSC1
0
0
1
1
Bit
7
6
5 to 0
Bit
Symbol
MOSI
MISO
SPCTL - SPI control register (address D5H) bit descriptions
SPCTL - SPI control register (address D5H) clock rate selection
SPCFG - SPI status register (address AAH) bit allocation
SPCFG - SPI status register (address AAH) bit descriptions
Symbol
CPHA
PSC1
PSC0
Symbol
SPIF
WCOL
-
SPIF
7
MSB
MSB
1
Rev. 05 — 15 December 2009
WCOL
2
6
6
Description
Clock Phase control bit. 1 = shift triggered on the trailing edge of the
clock; 0 = shift triggered on the leading edge of the clock.
SPI Clock Rate Select bit 1. Along with PSC0 controls the SPICLK rate
of the device when a master. PSC1 and PSC0 have no effect on the
slave. See
SPI Clock Rate Select bit 0. Along with PSC1 controls the SPICLK rate
of the device when a master. PSC1 and PSC0 have no effect on the
slave. See
Description
SPI interrupt flag. Upon completion of data transfer, this bit is set to ‘1’.
If SPIE = 1 and ES = 1, an interrupt is then generated. This bit is
cleared by software.
Write Collision Flag. Set if the SPI data register is written to during data
transfer. This bit is cleared by software.
Reserved for future use. Should be set to ‘0’ by user programs.
6
3
PSC0
0
1
0
1
5
5
5
Table
Table
-
4
4
4
30.
30.
5
P89LV51RB2/RC2/RD2
3
3
4
-
6
2
2
8-bit microcontrollers with 80C51 core
7
1
1
3
-
LSB
LSB
8
SPICLK = f
4
16
64
128
2
-
002aaa529
…continued
osc
© NXP B.V. 2009. All rights reserved.
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