P89LV51RD2BBC NXP Semiconductors, P89LV51RD2BBC Datasheet - Page 29

• Manufacturer Part Number: P89LV51RD2BBC
• Description: MCU 8-Bit 89LV 80C51 CISC 64KB Flash 3.3V 44-Pin TQFP Tray
• Manufacturer: NXP Semiconductors

Specifications of P89LV51RD2BBC

• Package: 44TQFP
• Device Core: 80C51
• Family Name: 89LV
• Maximum Speed: 40 MHz
• Ram Size: 1 KB
• Program Memory Size: 64 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 32
• Interface Type: SPI/UART
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

NXP Semiconductors
P89LV51RB2_RC2_RD2_5
Product data sheet
6.4.1 Mode 0
6.4.2 Mode 1
Table 18.
Putting either Timer into mode 0 makes it look like an 8048 Timer, which is an 8-bit
counter with a fixed divide-by-32 prescaler.
In this mode, the Timer register is configured as a 13-bit register. As the count rolls over
from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the
Timer when TRn = 1 and either GATE = 0 or INTn = 1. Setting GATE = 1 allows the Timer
to be controlled by external input INTn, to facilitate pulse width measurements. TRn is a
control bit in the Special Function Register TCON
register.
The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper
3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not
clear the registers.
Mode 0 operation is the same for Timer 0 and Timer 1 (see
different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).
Mode 1 is the same as mode 0, except that all 16 bits of the timer register (THn and TLn)
are used. See
Bit
2
1
0
Fig 7. Timer/counter 0 or 1 in mode 0 (13-bit counter)
INTn pin
TnGate
Tn pin
osc/6
TRn
TCON - Timer/counter control register (address 88H) bit descriptions
Symbol
IT1
IE0
IT0
Figure
Rev. 05 — 15 December 2009
8.
Description
Interrupt 1 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 1.
Interrupt 0 Edge flag. Set by hardware when external interrupt 0
edge/low level is detected. Cleared by hardware when the interrupt is
processed, or by software.
Interrupt 0 Type control bit. Set/cleared by software to specify falling
edge/low level that triggers external interrupt 0.
C/T = 0
C/T = 1
P89LV51RB2/RC2/RD2
control
Figure 7
8-bit microcontrollers with 80C51 core
(Figure
(5-bits)
TLn
shows mode 0 operation.
6). The GATE bit is in the TMOD
(8-bits)
THn
Figure
overflow
7). There are two
© NXP B.V. 2009. All rights reserved.
TFn
002aaa519
…continued
interrupt
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