ST70235A STMicroelectronics, ST70235A Datasheet - Page 9

• Manufacturer Part Number: ST70235A
• Description: Transceiver 144-Pin TQFP
• Manufacturer: STMicroelectronics

Specifications of ST70235A

• Package: 144TQFP
• Power Supply Type: Analog
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62|3 V
• Maximum Operating Supply Voltage: 1.98|3.6 V
• Case: QFP

PIN SUMMARY (continued)
I
I-PU
I-PD
I-TTL
O
OZ
IO
BS cell = Boundary-Scan cell
O
B
C
Main Block Description
The following drawings describe the sequence of
functions performed by the chip.
DSP Front-End
The DSP Front-End contains 4 parts in the
receive direction: the Input Selector, the Analog
Front-End Interface, the Decimator and the Time
Equalizer.
The input selector is used internally to enable test
loopbacks inside the chip. The Analog Front-End
lnterface transfers 16-bit words, multiplexed on 4
input/output signals. Word transfer is carried out in
4 clock cycles.
The Decimator receives 16-bit samples at 8.8MHz
(as sent by the Analog Front-End chip: ST70134)
and reduces this rate to 2.2MHz.
The Time Equalizer (TEQ) module is a FIR filter
with programmable coefficients. Its main purpose
I
MISCELLANEOUS
GP_IN
GP_OUT
RESETB
TESTSE
IDDq
COMP_ROUT
DISABLE_COMP
Mnemonic
= Input, CMOS levels
= Input with pull-up resistance, TTL
= Input with pull-down resistance, TTL
= Input TTL levels
= Push-pull output
= Push-pull output with high-impedance
= Input / Tristate Push-pull output
= Input cell
= Output cell
= Bidirectional cell
= Clock
levels
levels
state
Type
I-PD
I-PD
O
O
I
I
I
BS Type
none
none
none
O
I
I
I
of Signals
Number
none
none
2
1
1
1
I
General purpose input
General purpose output
Hard reset
Enable scan test mode
Test pin, active high
Compensation cell resistor
Disable compensation cell
is
Interferences (ISI) by shortening the channel
impulse response.
Both the Decimator and TEQ can be bypassed. In
the
includes:
equalization and interpolation. The sidelobe
filtering and delay equalization are implemented
by IIR Filters, reducing the effect of echo in FDM
systems.
Clipping is a statistical process limiting the
amplitude of the output signal, optimizing the
dynamic range of the AFE. The interpolator
receives data at 2.2MHz and generates samples
at a rate of 8.8MHz.
DMT Modem
This module is a programmable DSP unit. Its
instruction set enables the basic functions of the
DMT algorithm like FFT, IFFT, Scaling, Rotor and
Frequency Equalization (FEQ) in compliance with
ANSI T1.413 specifications.
In the RX path, the 512-point FFT transforms the
time-domain DMT symbol into a frequency
domain representation which can be further
decoded by the subsequent demapping stages.
In other words, the Fast Fourier Transform
process is used to transform from time domain to
frequency domain (receive path). 1024 time
samples are processed. After the first stage time
domain equalization and FFT block an ICI
(InterCarrier Interference) free information stream
turns out.
to
transmit direction, the
reduce
sidelobe
Function
the
filtering,
effect
of
DSP Front-End
clipping,
Inter-Symbol
ST70235A
delay
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