ST70235A STMicroelectronics, ST70235A Datasheet - Page 13

• Manufacturer Part Number: ST70235A
• Description: Transceiver 144-Pin TQFP
• Manufacturer: STMicroelectronics

Specifications of ST70235A

• Package: 144TQFP
• Power Supply Type: Analog
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62|3 V
• Maximum Operating Supply Voltage: 1.98|3.6 V
• Case: QFP

DMT Symbol Timing Unit (DSTU)
The DSTU interfaces with various modules, like
DSP FrontEnd, FFT/IFFT, Mapper/Demapper, RS,
Monitor and Transceiver Controller. It consists of a
real time and a scheduler modules.
The real time unit generates a timebase for the
DMT symbols (sample counter), superframes
(symbol
counter). The timebases can be modified by
various control features. They are continuously
fine-tuned by the DPLL module.
The DSTU schedulers execute a program,
controlled by program opcodes and a set of
variables, the most important of which are real
time counters.
The
completely
programs. An independent set of variables is
assigned to each of them. The sequencer
programs can be updated in real time.
ST70235A interfaces
Overview
See Figure 9.
Processor Interface (ATC)
The ST70235A is controlled and configured by an
external processor across the processor interface.
All programmable coefficients and parameters are
loaded through this path.
Figure 10 : Generic Processor Interface Write Timing Cycle
1: RDB = WR_RDB is high.
transmit
ALE
CSB
Address/DATA
WRB
RDYB
MClk
counter)
1
independent
and
and
receive
hyper-frames
T
and
ale2cs
sequencers
T
alew
T
run
avs
T
cs2wr
T
avh
different
(sync
are
T
wr2rdy
T
Data and addresses are multiplexed
ST70235A works in 16 bits data access, so
address bit 0 is not used. Address bit 1 is not
multiplexed with data. It has its own pin : BE1.
Byte access are not supported. Access cycle read
or write are always in 16 bits data wide, ie bit
address A0 is always zero value.
The interrupt request pin to the processor is INTB,
and is an Open Drain output.
The ST70235A supports both little and big endian.
The default feature is big endian.
Figure 9 : ST70235A Interfaces
Generic Interface
This interface is suitable for a number of
processors using a multiplexed Address/data bus.
In this case, synchronization of the input signals
with PCLK pin is not necessary.
wr2Mclk
T
wr2d
T
RESET
CLOCK
JTAG
csre
AFE INTERFACE TO ADSL LINE (ST70134)
DIGITAL INTERFACE UTOPIA
ST70235A
T
rdy2cs
T
rdy2wr
T
mclk
PROCESSOR
INTERFACE
(ATC)
ST70235A
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