RFW-D100 Vishay, RFW-D100 Datasheet - Page 21

• Manufacturer Part Number: RFW-D100
• Manufacturer: Vishay

Specifications of RFW-D100

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Package Type: LQFP
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Lead Free Status / Rohs Status: Supplier Unconfirmed

SYSTEM CONTROL REGISTER 4 (SCR4)
This register is a read/write register.
Bit 0: IE
This flag enables all interrupts when set to ‘1’.
When ‘0’, all interrupts are disabled.
Bit 1: RF_ACTIVE
This bit controls RF_ACTIVE output pin.
When this bit is high, the RF_ACTIVE output pin is
high.
When this bit is low, the RF_ACTIVE output pin is low.
It controls the RFW122 ACT pin, enabling the RFW122
either to active mode or standby mode.
Bit 2: WIN CONT
Determines the size of the WINDOW in the
PREAMBLE search module.
If (BLR + 6) > 14 and WIN_CONT=1, then the
preamble window size is 5 samples.
If (BLR + 6) < 14 or WIN_CONT=0, then the preamble
window size is 3 samples.
Bit 3: FIFO FLAGS
Determines the RX_FIFO AF flags and the TX_FIFO
AE flag:
If FIFO_FLAGS=0, then AF=12 and AE=4.
If FIFO_FLAGS=1, then AF=8 and AE=8.
RX_AF
(exceptions are described in the RX_FIFO chapter).
TX_AE interrupt is invoked when RFSR=AE.
Default Value: 0 x 00.
Bits 0,1: NODE_LOC [0:1]
These bits determine the location of the NODE_ID
parameter in the header (the location is specified in
bytes excluding preamble). The location should be
fixed for all of the different kinds of packets transferred
by the network.
Document Number 84675
Rev. 1.1, 22-Jan-07
NODE_ID Location
Name
Name
SCR4
LCR
2
3
4
5
interrupt
Bit 7
Bit 7
is
NODE LOC 1
invoked
0
0
1
1
SIZE LOC 2
Bit 6
Bit 6
For more information please contact: [e-mail]
when
NODE LOC 0
SIZE LOC 1
Bit 5
Bit 5
RFSR=AF
0
1
0
1
SIZE LOC 0
Bit 4
BIt 4
Transmit FIFO Status Register (TFSR)
This register is a read-only register.
Contains the number of bytes in the TX_FIFO.
Default Value: 0 x 00 (TX_FIFO empty).
Receive FIFO Status Register (RFSR)
This register is a read only register.
Contains the number of bytes in the RX_FIFO.
Default Value: 0 x 00 (TR_FIFO empty).
Location Control Register (LCR)
This is a read/write register.
This register determines the location of fields NET_ID,
NODE_ID, and PACKET_SIZE in the packet structure.
PPR[6] determines whether the packet size is fixed or
variable.
PPR[7] determines whether NODE_ID is enabled/
disabled.
PPR[8] determines whether NET_ID is enabled/
disabled.
If two or three of the following are enabled:
then the following relative values must be kept:
NET_ID location < NODE_ID location < Size Location.
NODE_ID location in the packet header must always
come after NET_ID location.
Bits 2, 3: NET_LOC [0:1]
These bits determine the location of the NET_ID
parameter in the header (the location is specified in
bytes excluding PREAMBLE). The location should be
fixed for all the different kinds of packets transferred by
the network.
NET_ID location in the packet header must always be
before NODE_ID location.
• Variable packet size
• NET_D filter enabled
• NODE_ID filter enabled
FIFO FLAGS
NET LOC 1
Bit 3
Bit 3
NET LOC 0
WIN CONT
BIt 2
Bit 2
NODE LOC 1 NODE LOC 0
Vishay RFWaves
RF_ACTIVE
Bit 1
Bit1
RFW-D100
www.vishay.com
Bit 0
Bit 0
IE
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