TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 134

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Ed. 3, December 2000
QE1M
TXC-04252
TXC-04252-MB
Note 1: In determining whether to send TC ODI or TC RDI, it is necessary to sample certain alarm conditions. Since
0B1 Port 3
0E1 Port 4
0B2 Port 3
0E2 Port 4
051 Port 1
081 Port 2
052 Port 1
082 Port 2
Address
(cont.)
TC ODI or TC RDI are sent only once for every 38 ms multiframe, it is conceivable that these alarms may tog-
gle more than one time in this interval. Therefore, all the alarms needed to generate TC ODI or TC RDI are
sampled during every 500 s multiframe, setting the TC ODI or TC RDI alarm.
5-2
Bit
2
1
0
7
6
1
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
TCnAEN
RnSETS
RnSETC
Symbol
TnRDIC
Unused
TCnOE
TnFB2
Tandem Connection Outgoing Defect Indication Enable for Port n: As
explained in Note 1, a 1 enables internal defined tandem connection alarms
to send a TC ODI (bit 7 in frame 74). For example, a TC ODI for port 1 is
generated:
- When TC enable (TC1EN) and TC ODI enable (TC1OE) are 1 and
- When TC enable (TC1EN) is a 1 and TC ODI enable (TC1OE) is 0 and:
Tandem Connection Line AIS Enable for Port n: A 1 enables internal
receive TC alarms to generate receive E1 line AIS.
Transmit Port n RDIC (Remote Connectivity Defect Indication):
A 1 enables an RDIC to be transmitted (bit 8 in the V5 byte is set to 1, and
bits 5, 6 and 7 in the K4 (Z7) byte are set to 110).
Reset Port n Selected Functions: A 1 will clear the alarms, reset the per-
formance counters to 0, and re-initialize the FIFOs associated with port n.
The control bits for port n are not reset. This bit is self-clearing, and will
reset to 0 after the reset cycle is completed.
Reset Port n Performance Counters: A 1 resets the performance
counters to 0 for port n. This bit is self-clearing, and will reset to 0 after the
reset cycle is completed.
Unused: These bits must be written to 0.
Transmit Port n BIP-2 Error Mask (Force BIP-2 Error): A 1 causes bits 1
and 2 (the BIP-2 value) in the V5 byte to be inverted from the calculated
value and transmitted for one frame. This bit is self-clearing, and will reset
to 0 after the single error is transmitted.
any of:
- Loss Of Pointer Alarm (A1LOP , B1LOP)
- TU AIS Alarm (A1AIS, B1AIS)
- Drop Bus AIS Alarm (AsUASI, BsUASI) when HEAISE is 1
- Drop Bus H4 Alarm (AsDH4E, BsDH4E) when DV1SEL is 1
- Unequipped signal label (A1UNEQ, B1UNEQ) when UQAE is 1
- Mismatch signal label (A1SLER, B1SLER)
- J2 Loss Of Lock Alarm (A1J2LOL, B1J2LOL) when J2AISEN is 1
- J2 Mismatch Alarm (A1J2TIM, B1J2TIM) when J2AISEN is 1
- TC Unequipped Alarm (A1TCUQ, B1TCUQ)
- TC AIS alarm (A1TCAIS, B1TCAIS)
- TC Loss Of Lock Alarm (A1TCLL, B1TCLL)
- TC Mismatch Alarm (A1TCTM, B1TCTM)
- TC Loss Of Multiframe Alarm (A1TCLM, B1TCLM)
- A 1 written to TC1ODI.
- A 1 written to TC1ODI.
(where S is the STS-1 or AU-3 identifier, 1-3)
DATA SHEET
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