TXC-04252AIPQ Transwitch Corporation, TXC-04252AIPQ Datasheet - Page 114

• Manufacturer Part Number: TXC-04252AIPQ
• Manufacturer: Transwitch Corporation

Specifications of TXC-04252AIPQ

• Pin Count: 160
• Screening Level: Industrial
• Package Type: PQFP
• Lead Free Status / Rohs Status: Not Compliant

Ed. 3, December 2000
QE1M
TXC-04252
TXC-04252-MB
Note 1: Please refer to the tables in the Operation - Interrupt Structure section for the specific alarms and register
Address
021
locations to which these interrupt masks apply. RPTnA or RPTnB is not required to be set to 1 to enable
an interrupt for AnRFI or BnRFI alarms. Control bit HDWIE must be set to 1 if a hardware interrupt is required.
Bit
Proprietary TranSwitch Corporation Information for use Solely by its Customers.
7
6
5
4
3
2
1
0
ECKMSK
Symbol
ASMSK
BSMSK
Unused
P4MSK
P3MSK
P2MSK
P1MSK
Unused: This bit must be written to 0.
External Clock Interrupt Mask Bit: A 1 enables a hardware interrupt
and software interrupt indications (INT and ETXCK) when an external
clock failure alarm has occurred. See Note 1.
A Side Interrupt Mask Bit: A 1 enables the A Side Interrupt Indication
(ASIDE). See Note 1.
B Side Interrupt Mask Bit: A 1 enables the B Side Interrupt Indication
(BSIDE). See Note 1.
Port 4 Interrupt Mask Bit: A 1 enables the Port 4 Interrupt Indication
(PORT4). It permits a hardware interrupt and a software interrupt indica-
tion (INT) when an alarm has occurred in one of the alarm registers for
port 4, when the corresponding RPT4A, RPT4B, TFIFO4A, TFIFO4B,
RFIFO4 or TPORT4 mask bit is set to 1. See Note 1.
Port 3 Interrupt Mask Bit: A 1 enables the Port 3 Interrupt Indication
(PORT3). It permits a hardware interrupt and a software interrupt indica-
tion (INT) when an alarm has occurred in one of the alarm registers for
port 3, when the corresponding RPT3A, RPT3B, TFIFO3A, TFIFO3B,
RFIFO3 or TPORT3 mask bit is set to 1. See Note 1.
Port 2 Interrupt Mask Bit: A 1 enables the Port 2 Interrupt Indication
(PORT2). It permits a hardware interrupt and a software interrupt indica-
tion (INT) when an alarm has occurred in one of the alarm registers for
port 2, when the corresponding RPT2A, RPT2B, TFIFO2A, TFIFO2B,
RFIFO2 or TPORT2 mask bit is set to 1. See Note 1.
Port 1 Interrupt Mask Bit: A 1 enables the Port 1 Interrupt Indication
(PORT1). It permits a hardware interrupt and a software interrupt indica-
tion (INT) when an alarm has occurred in one of the alarm registers for
port 1, when the corresponding RPT1A, RPT1B, TFIFO1A, TFIFO1B,
RFIFO1 or TPORT1 mask bit is set to 1. See Note 1.
DATA SHEET
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Description