LPC2214FBD144 NXP Semiconductors, LPC2214FBD144 Datasheet - Page 18

• Manufacturer Part Number: LPC2214FBD144
• Manufacturer: NXP Semiconductors

Specifications of LPC2214FBD144

• Cpu Family: LPC2000
• Device Core: ARM7TDMI-S
• Device Core Size: 16/32Bit
• Frequency (max): 60MHz
• Interface Type: I2C/SPI
• Program Memory Type: Flash
• Program Memory Size: 256KB
• Total Internal Ram Size: 16KB
• # I/os (max): 112
• Number Of Timers - General Purpose: 2
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/2.5/3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: LQFP
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
LPC2212_2214_4
Product data sheet
6.11.1 Features
6.12.1 Features
6.12.2 Features available in LPC2212/2214/01 only
6.11 I
6.12 SPI serial I/O controller
The I
line (SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
I
The LPC2212/2214 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
2
2
C-bus).
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C-bus serial I/O controller
Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex communication.
Combined SPI master and slave.
Maximum data bit rate of
Eight to 16 bits per frame.
2
2
C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock
C-bus implemented in LPC2212/2214 supports a bit rate up to 400 kbit/s (Fast
2
C-bus may be used for test and diagnostic purposes.
2
C-bus compliant interface.
Rev. 04 — 3 January 2008
1
8
of the input clock rate.
2
C-bus is a multi-master bus; it can be
16/32-bit ARM microcontrollers
LPC2212/2214
© NXP B.V. 2008. All rights reserved.
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