TE28F160S375 Intel, TE28F160S375 Datasheet - Page 7

• Manufacturer Part Number: TE28F160S375
• Manufacturer: Intel

Specifications of TE28F160S375

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 75ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

A
DQ
DQ
CE
CE
RP#
OE#
WE#
WP#
BYTE#
V
V
GND
NC
STS
0
PP
CC
ADVANCE INFORMATION
–A
Sym
0
1
0
15
#,
#
–
21
OUTPUT
OUTPUT
SUPPLY BLOCK ERASE, PROGRAM, LOCK-BIT CONFIGURATION POWER SUPPLY:
SUPPLY DEVICE POWER SUPPLY: Do not float any power pins. Do not attempt block
SUPPLY GROUND: Do not float any ground pins.
INPUT/
INPUT
INPUT
INPUT
INPUT
INPUT
DRAIN
INPUT
INPUT
OPEN
Type
ADDRESS INPUTS: Address inputs for read and write operations are internally
latched during a write cycle. A
In x16 mode, A
DATA INPUTS/OUTPUTS: Inputs data and commands during CUI write cycles;
outputs data during memory array, Status Register, query and identifier code read
cycles. Data pins float to high-impedance when the chip is deselected or outputs
are disabled. Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. With CE
consumption reduces to standby levels. Both CE
the device. Device selection occurs with the latter falling edge of CE
first rising edge of CE
RESET/DEEP POWER-DOWN: When driven low, RP# inhibits write operations
which provides data protection during system power transitions, puts the device in
deep power-down mode, and resets internal automation. RP#-high enables normal
operation. Exit from deep power-down sets the device to read array mode.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data
are latched on the rising edge of the WE# pulse.
WRITE PROTECT: Master control for block locking. When V
cannot be erased or programmed, and block lock-bits cannot be set or cleared.
BYTE ENABLE: Configures x8 mode (low) or x16 mode (high).
Necessary voltage to perform block erase, program, and lock-bit configuration
operations. Do not float any power pins.
erase, program, or block-lock configuration with invalid V
NO CONNECT: Lead is not internally connected; it may be driven or floated.
STATUS: Indicates the status of the internal state machine. When configured in
level mode (default), it acts as a RY/BY# pin. For this and alternate configurations
of the STATUS pin, see the Configuration command. Tie STS to V
resistor.
16-Mbit
0
is not used; input buffer is off.
Table 1. Pin Descriptions
A
0
0
# or CE
–A
20
0
# or CE
0
1
32-Mbit
# disables the device.
Name and Function
selects high or low byte when operating in x8 mode.
1
# high, the device is deselected and power
A
0
–A
21
0
# and CE
CC
1
values.
28F160S3, 28F320S3
# must be low to select
IL
, locked blocks
CC
0
# or CE
with a pull-up
1
#. The
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