TE28F160S375 Intel, TE28F160S375 Datasheet - Page 28

• Manufacturer Part Number: TE28F160S375
• Manufacturer: Intel

Specifications of TE28F160S375

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 75ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S3, 28F320S3
attempted while V
SR.4 and SR.3 will be set to “1.” Successful
byte/word
corresponding block lock-bit be cleared. If a
byte/word
corresponding block lock-bit is set and WP# = V
SR.1 and SR.4 will be set to “1.”
4.10
The Status (STS) pin can be configured to different
states using the STS pin Configuration command.
Once the STS pin has been configured, it remains
in that configuration until another configuration
command is issued or RP# is low. Initially, the STS
pin defaults to level RY/BY# operation where STS
low indicates that the state machine is busy. STS
high indicates that the state machine is ready for a
new operation or suspended.
To reconfigure the Status (STS) pin to other modes,
the STS pin Configuration command is issued
followed by the desired configuration code. The
three alternate configurations are all pulse mode for
use as a system interrupt as described in Table 14.
For these configurations, bit 0 controls Erase
Complete interrupt pulse, and bit 1 controls Write
Complete interrupt pulse. When the device is
configured in one of the pulse modes, the STS pin
pulses low with a typical pulse width of 250 ns.
Supplying the 00h configuration code with the
Configuration command resets the STS pin to the
default RY/BY# level mode. Refer to Table 14 for
configuration coding definitions. The Configuration
command may only be given when the device is not
busy or suspended. Check SR.7 for device status.
An invalid configuration code will result in both
Status Register bits SR.4 and SR.5 being set to “1.”
4.11
The Block Erase Suspend command allows
block-erase interruption to read or program data in
another block of memory. Once the block erase
process starts, writing the Block Erase Suspend
command requests that the WSM suspend the
block erase sequence at a predetermined point in
the algorithm. The device outputs Status Register
data when read after the Block Erase Suspend
command is written. Polling Status Register bit
28
STS Configuration Command
Block Erase Suspend
Command
program
programming
PP
is
V
PPLK
attempted
, Status Register bits
requires
when
that
the
the
IL
,
SR.7 can determine when the block erase operation
has been suspended. When SR.7 = 1, SR.6 should
also be set to “1,” indicating that the device is in the
erase suspend mode. STS in level RY/BY# mode
will also transition to V
defines the block erase suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is
suspended. A Program command sequence can
also be issued during erase suspend to program
data in other blocks. Using the Program Suspend
command (see Section 4.12), a program operation
can also be suspended. During a program operation
with block erase suspended, Status Register bit
SR.7 will return to “0” and STS in RY/BY# mode will
transition to V
indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
will continue the block erase process. Status
register bits SR.6 and SR.7 will automatically clear
and STS in RY/BY# mode will return to V
the Erase Resume command is written, the device
automatically outputs Status Register data when
read (see Figure 11). V
and V
V
is suspended. RP# must also remain at V
same RP# level used for block erase). Block erase
cannot resume until program operations initiated
during block erase suspend have completed.
4.12
The Program Suspend command allows program
interruption to read data in other flash memory
locations. Once the programming process starts,
writing the Program Suspend command requests
that the WSM suspend the program sequence at a
predetermined point in the algorithm. The device
continues to output Status Register data when read
after the Program Suspend command is written.
Polling Status Register bits SR.7 can determine
when
suspended. When SR.7 = 1, SR.2 should also be
set to “1”, indicating that the device is in the
program suspend mode. STS in level RY/BY#
mode will also transition to V
t
WHRH1
CC
levels used for block erase) while block erase
CC
ADVANCE INFORMATION
defines the program suspend latency.
the
must remain at V
Program Suspend Command
programming
OL
. However, SR.6 will remain “1” to
PP
OH
CC1/2
must remain at V
. Specification t
operation
(the same V
OH
. Specification
has
OL
PP
IH
. After
WHRH2
PPH1/2
been
and
(the