TE28F160S375 Intel, TE28F160S375 Datasheet - Page 46

• Manufacturer Part Number: TE28F160S375
• Manufacturer: Intel

Specifications of TE28F160S375

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 75ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 2.7/3.3/5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

28F160S3, 28F320S3
6.2.5
NOTES:
1.
2.
3.
4.
5.
6.
46
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
#
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics for read-only operations.
Sampled, not 100% tested.
Refer to Table 3 for valid A
V
See Ordering Information for device speeds (valid operational combinations).
See Figures 14 through 16 for testing characteristics.
PP
should be at V
t
t
( t
t
( t
t
t
t
( t
t
t
t
t
t
t
t
t
t
( t
PHWL
ELWL
WLWH
DVWH
AVWH
WHEH
WHDX
WHAX
WHWL
SHWH
VPWH
WHGL
WHRL
QVSL
QVVL
WLEL
ELEH
EHWH
EHEL
AC CHARACTERISTICS - WRITE OPERATIONS
Sym
)
( t
)
( t
( t
( t
( t
( t
)
( t
( t
( t
)
PHEL
EHRL
DVEH
AVEH
EHDX
EHAX
SHEH
VPEH
EHGL
PPH1/2
)
) Address Setup to WE# (CE
) Address Hold from WE# (CE
) V
)
) Write Recovery before Read
) Data Setup to WE# (CE
) Data Hold from WE# (CE
) WP# V
Table 21. Write Operations
RP# High Recovery to WE# (CE
CE
(WE# Setup to CE
WE# Pulse Width
(CE
CE
(WE# Hold from CE
WE# Pulse Width High
(CE
WE# High to STS in RY/BY# Low
WP# V
V
Versions
PP
PP
until determination of block erase, program, or lock-bit configuration success (SR.1/3/4/5 = 0).
X
X
IN
X
X
# Setup to WE# Going Low
# Hold from WE# High
Setup to WE# (CE
Hold from Valid SRD, STS in RY/BY# High
# Pulse Width)
# Pulse Width High)
and D
IH
IH
Setup to WE# (CE
Hold from Valid SRD
IN
(5)
for block erase, program, or lock-bit configuration.
Parameter
X
# Going Low)
X
# High)
X
X
# ) Going High
# ) Going High
X
# ) High
X
X
# ) Going High
X
# ) Going High
(1,5,6)
# ) High
X
#) Going Low
, T
A
= –40°C to +85°C
2.7V–3.6V V
ADVANCE INFORMATION
3.3V ± 0.3V,
Notes
2,4
2,4
2
3
3
2
CC
Min
Valid for All
100
100
10
50
70
50
50
10
30
25
1
0
0
5
5
0
0
0
Speeds
Max
100
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns