SC68C562C1A NXP Semiconductors, SC68C562C1A Datasheet - Page 7

• Manufacturer Part Number: SC68C562C1A
• Manufacturer: NXP Semiconductors

Specifications of SC68C562C1A

• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
2004 Mar 29
DONEN
RTSA/BN,
SYNOUTA/BN
DTACKN
DTC
V
GND
CC
CMOS Dual universal serial communications controller
(CDUSCC)
MNEMONIC
26, 13,
34, 52
45, 9
41, 7
PIN
29
24
25
TYPE
I/O
O
O
I
I
I
Data Transfer Acknowledge: Active-LOW, 3-state. DTACKN is asserted on a write cycle to indicate
indicated by the assertion of DTCN or negation of DMA acknowledge inputs (whichever occurs first),
Done: Active-LOW, open-drain. DONEN can be used and is active in both DMA and non-DMA
modes. As an input, DONEN indicates the last DMA transfer cycle to the TxFIFO. As an output,
DONEN indicates either the last DMA transfer from the RxFIFO or that the transmitted character
count has reached terminal count.
Channel A (B) Sync Detect or Request-to-Send: Active-LOW. If programmed as a sync output, it
is asserted one bit time after the specified sync character (COP or BISYNC modes) or a FLAG
(BOP modes) is detected by the receiver. As a Request-to-Send modem control signal, it functions
as described previously for the TxDRQN/RTSN pin.
that the data on the bus has been latched, and on a read cycle or interrupt acknowledge cycle to
indicate valid data is on the bus. In a write bus cycle, input data is latched by the assertion (falling
edge) of DTACKN or by the negation (rising edge) of CSN, whichever occurs first. The signal is
negated when completion of the cycle is indicated by negation of CSN or IACKN input, and returns
to the inactive state (3-state) a short period after it is negated. In single address DMA mode, input
data is latched by the assertion (falling edge) of DTCN or by the negation (rising edge) of the DMA
acknowledge input, whichever occurs first. DTACK is negated when completion of the cycle is
and returns to the inactive state (3-state) a short period after it is negated. When inactive, DTACKN
requires an external pull-up resistor.
Device Transfer Complete: Active-LOW. DTCN is asserted by the DMA controller to indicate that
the requested data transfer is complete.
+5V Power Input
Signal and Power Ground Input
7
NAME AND FUNCTION
SC68C562
Product data