SC68C562C1A NXP Semiconductors, SC68C562C1A Datasheet - Page 3

• Manufacturer Part Number: SC68C562C1A
• Manufacturer: NXP Semiconductors

Specifications of SC68C562C1A

• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: PLCC
• Mounting: Surface Mount
• Pin Count: 52
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
Character-Oriented Protocol Features
BISYNC Features
ORDERING INFORMATION
V
ABSOLUTE MAXIMUM RATINGS
2004 Mar 29
Type number
SC68C562C1A
T
T
V
V
CC
SYMBOL
Parity, overrun, and framing error detection
False start bit detection
Start bit search 1/2-bit time after framing error detection
Break generation with handshake for counting break characters
Detection of start and end of received break
Character compare with optional interrupt on match
Transmits up to 10 Mb/s at 1X and receive up to 1 Mb/s at 16X
data rates
Character length: 5 to 8 bits
Odd or even parity, no parity, or force parity
LRC or CRC generation and checking
Optional opening PAD transmission
One or two SYN characters
External sync capability
SYN detection and optional stripping
SYN or MARK line fill on underrun
Idle in MARK or SYNs
Parity, FCS, overrun, and underrun error detection
EBCDIC or ASCII header, text and control messages
SYN, DLE stripping
EOM (end of message) detection and transmission
Auto transparent mode switching
amb
stg
CC
S
CMOS Dual universal serial communications controller
(CDUSCC)
= +5V
10 %; T
Operating ambient temperature
Storage temperature
Voltage from V
Voltage from any pin to ground
amb
Package
Name
PLCC52
= 0 C to +70 C. Serial data rate = 10 Mb/s
CC
to GND
3
Description
plastic leaded chip carrier; 52 leads; pedestal
1
PARAMETER
3
2
3
Bit-Oriented Protocol Features
Auto hunt after receipt of EOM sequence (with closing PAD check
after EOT or NAK)
Control character sequence detection for both transparent and
normal text
Character length: 5 to 8 bits
Detection and transmission of residual character: 0–7 bits
Automatic switch to programmed character length for I field
Zero insertion and deletion
Optional opening PAD transmission
Detection and generation of FLAG, ABORT, and IDLE bit patterns
Detection and generation of shared (single) FLAG between
frames
Detection of overlapping (shared zero) FLAGs
ABORT, ABORT-FLAGs, or FCS FLAGs line fill on underrun
Idle in MARK or FLAGs
Secondary address recognition including group and global
address
Single- or dual-octet secondary address
Extended address and control fields
Short frame rejection for receiver
Detection and notification of received end of message
CRC generation and checking
SDLC loop mode capability
–0.5 to V
–65 to +150
–0.5 to +7.0
RATING
0 to +70
CC
+0.5
SC68C562
Version
SOT238-3
Product data
UNIT
V
V
C
C