M29W800AT90M1 Micron Technology Inc, M29W800AT90M1 Datasheet - Page 9

• Manufacturer Part Number: M29W800AT90M1
• Manufacturer: Micron Technology Inc

Specifications of M29W800AT90M1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SO
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Supplier Unconfirmed

SIGNAL DESCRIPTIONS
See
Names.
Address Inputs (A0-A18). The address inputs
for the memory array are latched during a write op-
eration on the falling edge at Chip Enable E or
Write Enable W. In Word-wide organisation the
address lines are A0-A18, in Byte-wide organisa-
tion DQ15A–1 acts as an additional LSB address
line. When A9 is raised to V
tronic Signature Manufacturer or Device Code,
Block Protection Status or a Write Block Protection
or Block Unprotection is enabled depending on the
combination of levels on A0, A1, A6, A12 and A15.
Data Input/Outputs (DQ0-DQ7). These
Outputs are used in the Byte-wide and Word-wide
organisations. The input is data to be programmed
in the memory array or a command to be written to
the C.I. Both are latched on the rising edge of Chip
Enable E or Write Enable W. The output is data
from the Memory Array, the Electronic Signature
Manufacturer or Device codes, the Block Protec-
tion Status or the Status register Data Polling bit
DQ7, the Toggle Bits DQ6 and DQ2, the Error bit
DQ5 or the Erase Timer bit DQ3. Outputs are valid
when Chip Enable E and Output Enable G are ac-
tive. The output is high impedance when the chip
is deselected or the outputs are disabled and
when RP is at a Low level.
Data Input/Outputs (DQ8-DQ14 and DQ15A–
1). These Inputs/Outputs are additionally used in
the Word-wide organisation. When BYTE is High
DQ8-DQ14 and DQ15A–1 act as the MSB of the
Data Input or Output, functioning as described for
DQ0-DQ7 above, and DQ8-DQ15 are 'don't care'
for command inputs or status outputs. When
BYTE is Low, DQ0-DQ14 are high impedance,
DQ15A–1 is the Address A–1 input.
Chip Enable (E). The Chip Enable input acti-
vates the memory control logic, input buffers, de-
coders and sense amplifiers. E High deselects the
memory and reduces the power consumption to
the stan-by level. E can also be used to control
writing to the command register and to the memo-
ry array, while W remains at a low level. The Chip
Enable must be forced to V
protection operation.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read op-
eration. When G is High the outputs are High im-
pedance. G must be forced to V
Block Protection and Unprotection operations.
Figure 2., Logic Diagram
ID
ID
, either a Read Elec-
during the Block Un-
and
Table 1., Signal
ID
level during
Inputs/
Write Enable (W). This input controls writing to
the Command Register and Address and Data
latches.
Byte/Word Organization Select (BYTE). The BYTE
input selects the output configuration for the de-
vice: Byte-wide (x8) mode or Word-wide (x16)
mode. When BYTE is Low, the Byte-wide mode is
selected and the data is read and programmed on
DQ0-DQ7. In this mode, DQ8-DQ14 are at high
impedance and DQ15A–1 is the LSB address.
When BYTE is High, the Word-wide mode is se-
lected and the data is read and programmed on
DQ0-DQ15.
Ready/Busy Output (RB). Ready/Busy
open-drain output and gives the internal state of
the P/E.C. of the device. When RB is Low, the de-
vice is Busy with a Program or Erase operation
and it will not accept any additional program or
erase instructions except the Erase Suspend in-
struction. When RB is High, the device is ready for
any Read, Program or Erase operation. The RB
will also be High when the memory is put in Erase
Suspend or Stan-by modes.
Reset/Block Temporary Unprotect Input (RP).
The RP Input provides hardware reset and pro-
tected block(s) temporary unprotection functions.
Reset of the memory is achieved by pulling RP to
V
en, if the memory is in Read or Stan-by modes, it
will be available for new operations in t
the rising edge of RP. If the memory is in Erase,
Erase Suspend or Program modes the reset will
take t
at V
ed by the rising edge of RB. A hardware reset dur-
ing an Erase or Program operation will corrupt the
data being programmed or the sector(s) being
erased. See Tables
teristics and
Waveforms.
Temporary block unprotection is made by holding
RP at V
blocks can be programmed or erased. The transi-
tion of RP from V
PHH
Characterisics and
AC
V
protected.
V
operations (Read, Program and Erase).
V
measurements.
IL
IH
CC
SS
for at least t
.
all blocks temporarily unprotected will be again
IL
Waveforms. When RP is returned from V
Ground. V
Supply Voltage. The power supply for all
. The end of the memory reset will be indicat-
PLYH
See
ID
. In this condition previously protected
during which the RB signal will be held
Tables
Figure 13., Data Polling DQ7 AC
PLPX
SS
M29W800AT, M29W800AB
IH
is the reference for all voltage
Figure 13., Data Polling DQ7
. When the reset pulse is giv-
15
to V
17
and 16, Read AC Charac-
ID
and
must slower than t
18,
Write
PHEL
is
after
ID
9/40
AC
PH-
an
to