M29W800AT90M1 Micron Technology Inc, M29W800AT90M1 Datasheet - Page 10

• Manufacturer Part Number: M29W800AT90M1
• Manufacturer: Micron Technology Inc

Specifications of M29W800AT90M1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SO
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Supplier Unconfirmed

M29W800AT, M29W800AB
DEVICE OPERATIONS
See
5., Read Electronic Signature (following AS in-
struction or with A9 = V
Block Protection with AS
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Sig-
nature, the Status Register or the Block Protection
Status. Both Chip Enable E and Output Enable G
must be low in order to read the output of the mem-
ory. A new operation is initiated either on the fol-
lowing edge of Chip Enable E or on any address
transition with E at V
Write. Write operations are used to give Instruc-
tion Commands to the memory or to latch input
data to be programmed. A write operation is initi-
ated when Chip Enable E is Low and Write Enable
W is Low with Output Enable G High. Addresses
are latched on the falling edge of W or E whichever
occurs last. Commands and Input Data are
latched on the rising edge of W or E whichever oc-
curs first.
Output Disable. The data outputs are high im-
pedance when the Output Enable G is High with
Write Enable W High.
Stan-by. The memory is in stan-by when Chip
Enable E is High and the P/E.C. is idle. The power
consumption is reduced to the stan-by level and
the outputs are high impedance, independent of
the Output Enable G or Write Enable W inputs.
Automatic Stan-by. After 150ns of bus inactivity
(no address transition, CE = V
levels are driving the addresses, the chip automat-
ically enters a pseudo-stan-by mode where con-
sumption is reduced to the CMOS stan-by value,
while outputs still drive the bus (if G = V
Electronic Signature. Two codes identifying the
manufacturer and the device can be read from the
memory. The manufacturer's code for STMicro-
electronics is 20h, the device code is D7h for the
M29W800AT (Top Boot) and 5Bh for the
M29W800AB (Bottom Boot). These codes allow
programming equipment or applications to auto-
matically match their interface to the characteris-
tics of the M29W800A. The Electronic Signature is
output by a Read operation when the voltage ap-
plied to A9 is at V
The manufacturer code is output when the Ad-
dress input A0 is Low and the device code when
this input is High. Other Address inputs are ig-
nored. The codes are output on DQ0-DQ7.
10/40
Table 4., User Bus Operations
ID
and address inputs A1 is Low.
IL
.
Instruction.
ID
)
and
IL
) and when CMOS
Table 6., Read
IL
(1)
).
,
Table
The Electronic Signature can also be read, without
raising A9 to V
struction AS. If the Byte-wide configuration is se-
lected the codes are output on DQ0-DQ7 with
DQ8-DQ14 at High impedance; if the Word-wide
configuration is selected the codes are output on
DQ0-DQ7 with DQ8-DQ15 at 00h.
Block Protection. Each block can be separately
protected against Program or Erase on program-
ming equipment. Block protection provides addi-
tional data security, as it disables all program or
erase operations. This mode is activated when
both A9 and G are raised to V
the block is applied on A12-A18. Block protection
is initiated on the edge of W falling to V
ter a delay of 100µs, the edge of W rising to V
ends the protection operations. Block protection
verify is achieved by bringing G, E, A0 and A6 to
V
Under these conditions, reading the data output
will yield 01h if the block defined by the inputs on
A12-A18 is protected. Any attempt to program or
erase a protected block will be ignored by the de-
vice.
Block Temporary Unprotection. Any previously
protected block can be temporarily unprotected in
order to change stored data. The temporary un-
protection mode is activated by bringing RP to V
During the temporary unprotection mode the pre-
viously protected blocks are unprotected. A block
can be selected and data can be modified by exe-
cuting the Erase or Program instruction with the
RP signal held at V
all the previously protected blocks are again pro-
tected.
Block Unprotection. All protected blocks can be
unprotected on programming equipment to allow
updating of bit contents. All blocks must first be
protected before the unprotection operation. Block
unprotection is activated when A9, G and E are at
V
by the edge of W falling to V
10ms, the unprotection operation will end. Unpro-
tection verify is achieved by bringing G and E to
V
remains at V
output data will yield 00h if the block defined by the
inputs A12-A18 has been successfully unprotect-
ed. Each block must be separately verified by giv-
ing its address in order to ensure that it has been
unprotected.
IL
ID
IL
and A1 to V
while A0 is at V
and A12, A15 at V
ID
. In these conditions, reading the
IH
ID
, while W is at V
, by giving the memory the In-
IL
ID
, A6 and A1 are at V
. When RP is returned to V
IH
. Unprotection is initiated
ID
IL
and an address in
. After a delay of
IH
and A9 at V
IL
. Then af-
IH
and A9
ID
ID
IH
IH
.
.
,