M29W800AT90M1 Micron Technology Inc, M29W800AT90M1 Datasheet - Page 6

• Manufacturer Part Number: M29W800AT90M1
• Manufacturer: Micron Technology Inc

Specifications of M29W800AT90M1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SO
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Supplier Unconfirmed

M29W800AT, M29W800AB
Command Interface
Instructions, made up of commands written in cy-
cles, can be given to the Program/Erase Controller
through a Command Interface (C.I.). For added
data protection, program or erase execution starts
after 4 or 6 cycles. The first, second, fourth and
fifth cycles are used to input Coded cycles to the
C.I. This Coded sequence is the same for all Pro-
gram/Erase Controller instructions. The 'Com-
mand' itself and its confirmation, when applicable,
are given on the third, fourth or sixth cycles. Any
incorrect command or any improper command se-
quence will reset the device to Read Array mode.
Instructions
Seven instructions are defined to perform Read
Array, Auto Select (to read the Electronic Signa-
ture or Block Protection Status), Program, Block
Erase, Chip Erase, Erase Suspend and Erase Re-
sume.
The internal P/E.C. automatically handles all tim-
ing and verification of the Program and Erase op-
erations. The Status Register Data Polling,
Toggle, Error bits and the RB output may be read
Figure 3. TSOP Connections
6/40
A15
A14
A13
A12
A11
A10
A18
A17
NC
NC
NC
NC
RP
RB
A9
A8
A7
A6
A5
A4
A3
A2
A1
W
1
12
13
24
M29W800T
M29W800B
AI02179
48
37
36
25
A16
BYTE
V SS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
V SS
E
A0
at any time, during programming or erase, to mon-
itor the progress of the operation.
Instructions are composed of up to six cycles. The
first two cycles input a Coded sequence to the
Command Interface which is common to all in-
structions (see Table 8).
The third cycle inputs the instruction set-up com-
mand. Subsequent cycles output the addressed
data, Electronic Signature or Block Protection Sta-
tus for Read operations. In order to give additional
data protection, the instructions for Program and
Block or Chip Erase require further command in-
puts. For a Program instruction, the fourth com-
mand cycle inputs the address and data to be
programmed. For an Erase instruction (Block or
Chip), the fourth and fifth cycles input a further
Coded sequence before the Erase confirm com-
mand on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data
from another block or to program data in another
block, and then resumed. When power is first ap-
plied or if V
terface is reset to Read Array.
Figure 4. SO Connections
DQ10
DQ11
V SS
DQ0
DQ8
DQ1
DQ9
DQ2
DQ3
A18
A17
RB
A7
A6
A5
A4
A3
A2
A1
A0
G
CC
E
falls below V
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
M29W800T
M29W800B
LKO
AI02181
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
, the command in-
RP
W
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYTE
V SS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V CC