M29W800AT90M1 Micron Technology Inc, M29W800AT90M1 Datasheet - Page 5

• Manufacturer Part Number: M29W800AT90M1
• Manufacturer: Micron Technology Inc

Specifications of M29W800AT90M1

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: SO
• Program/erase Volt (typ): 2.7 to 3.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Supplier Unconfirmed

DESCRIPTION
The M29W800A is a non-volatile memory that may
be erased electrically at the block or chip level and
programmed in-system on a Byte-by-Byte or
Word-by-Word basis using only a single 2.7V to
3.6V V
tions the necessary high voltages are generated
internally. The device can also be programmed in
standard programmers.
The array matrix organisation allows each block to
be erased and reprogrammed without affecting
other blocks. Blocks can be protected against pro-
graming and erase on programming equipment,
and temporarily unprotected to make changes in
the application. Each block can be programmed
and erased over 100,000 cycles.
Instructions for Read/Reset, Auto Select for read-
ing the Electronic Signature or Block Protection
status, Programming, Block and Chip Erase,
Erase Suspend and Resume are written to the de-
vice in cycles of commands to a Command Inter-
face using standard microprocessor write timings.
The device is offered in TSOP48 (12 x 20mm),
SO44 and TFBGA48 0.8 mm ball pitch packages.
Table 1. Signal Names
Organisation
The M29W800A is organised as 1M x8 or 512K
x16 bits selectable by the BYTE signal. When
BYTE is Low the Byte-wide x8 organisation is se-
lected and the address lines are DQ15A–1 and
A0-A18
DQ0-DQ7
DQ8-DQ14
DQ15A–1
E
G
W
RP
RB
BYTE
V
V
NC
DU
CC
SS
CC
supply. For Program and Erase opera-
Address Inputs
Data Input/Outputs, Command Inputs
Data Input/Outputs
Data Input/Output or Address Input
Chip Enable
Output Enable
Write Enable
Reset/Block Temporary Unprotect
Ready/Busy Output
Byte/Word Organization
Supply Voltage
Ground
Not Connected Internally
Don’t Use as Internally Connected
A0-A18. The Data Input/Output signal DQ15A–1
acts as address line A–1 which selects the lower
or upper Byte of the memory word for output on
DQ0-DQ7, DQ8-DQ14 remain at High impedance.
When BYTE is High the memory uses the address
inputs A0-A18 and the Data Input/Outputs DQ0-
DQ15. Memory control is provided by Chip Enable
E, Output Enable G and Write Enable W inputs.
A Reset/Block Temporary Unprotection RP tri-lev-
el input provides a hardware reset when pulled
Low, and when held High (at V
protects blocks previously protected allowing them
to be programed and erased. Erase and Program
operations are controlled by an internal Program/
Erase Controller (P/E.C.). Status Register data
output on DQ7 provides a Data Polling signal, and
DQ6 and DQ2 provide Toggle signals to indicate
the state of the P/E.C operations. A Ready/Busy
RB output indicates the completion of the internal
algorithms.
Memory Blocks
The devices feature asymmetrically blocked archi-
tecture providing system memory integration. Both
M29W800AT and M29W800AB devices have an
array of 19 blocks, one Boot Block of 16 KBytes or
8 KWords, two Parameter Blocks of 8 KBytes or 4
KWords, one Main Block of 32 KBytes or 16
KWords and fifteen Main Blocks of 64 KBytes or
32 KWords. The M29W800AT has the Boot Block
at the top of the memory address space and the
M29W800AB locates the Boot Block starting at the
bottom. The memory maps are showed in Tables
2
Each block can be erased separately, any combi-
nation of blocks can be specified for multi-block
erase or the entire chip may be erased. The Erase
operations are managed automatically by the P/
E.C. The block erase operation can be suspended
in order to read from or program to any block not
being erased, and then resumed.
Block protection provides additional data security.
Each block can be separately protected or unpro-
tected against Program or Erase on programming
equipment. All previously protected blocks can be
temporarily unprotected in the application.
Bus Operations
The following operations can be performed using
the appropriate bus cycles: Read (Array, Electron-
ic Signature, Block Protection Status), Write com-
mand, Output Disable, Stan-by, Reset, Block
Protection, Unprotection, Protection Verify, Unpro-
tection Verify and Block Temporary Unprotection.
See
ing AS instruction or with A9 = V
6., Read Block Protection with AS
and 3.
Table 5., Read Electronic Signature (follow-
M29W800AT, M29W800AB
ID
) temporarily un-
Instruction.
ID
)
and
Table
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