CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 94

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

13.0
CYNSE70256 has two separate power supplies, one for the core (V
13.1
Proper power-up sequence is required to correctly initialize the Cypress Network Search Engines before functional access to the
device can begin. RST_L and TRST_L should be held low before the power supplies ramp up. RST_L must be set low for a
duration of time afterward and then set high. The following steps describe the proper power-up sequence.
Document #: 38-02035 Rev. *E
1. Set RST_L and TRST_L low.
2. Power up V
3. RST_L should be held low for 0.5 ms (PLL lock time requirement). In CLK1X mode, the counting starts on the first rising edge
4. Continue to hold RST_L low for a minimum of 32 CLK1X cycles (when operating in CLK1X mode) or 64 CLK2X cycles (when
CLK2X mode. The order in which these signals (including V
of CLK1X after both V
rising edge of CLK2X when PHS_L is high, after both V
operating in CLK2X mode). Set RST_L to high afterward to complete the power-up sequence. For JTAG reset, TRST_L can
be brought high after V
Power-up Sequence
Power
DD
SADR[23:0]
CMD[10:2]
, V
CMD[1:0]
DDQ
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
Figure 12-12. SRAM Write Through Device Number 0 in Bank of Fifteen CYNSE70256
ACK
SSV
SSF
TLSZ = 10, HLAT = XXX, LRAM = 1, LDEV = 1
DQ
and start running CLK1X when operating in CLK1X mode or CLK2X and PHS_L when operating in
DD
DD
and V
and V
DDQ
0
1
1
1
z
0
0
DDQ
have reached their steady state voltages. In CLK2X mode, the counting starts on the first
have both reached their steady state voltages.
Address
cycle
Write
1
A B
01
Devices (Device Number 14 Timing)
cycle
2
x
cycle
3
DD
x
cycle
and V
4
DD
and V
cycle
DDQ
DD
5
) and another for the IOs (V
DDQ
have reached their steady state voltages.
cycle
6
) are applied is not critical.
cycle
7
1
cycle
8
z
z
z
z
cycle
9
1
1
1
cycle
DDQ
10
).
CYNSE70256
Page 94 of 109