CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 80

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

The logical 288-bit Search operation is shown in Figure 10-61. The entire table of 288-bit entries is compared to a 288-bit word
K that is presented on the DQ bus in cycles A, B, C, and D of the command using the GMR and local mask bits. The GMR is the
288-bit word specified by the two pairs of GMRs selected by the GMR Indexes in command cycles A and C in each of the fifteen
devices. The 288-bit word K that is presented on the DQ bus in cycles A, B, C, and D of the command is compared to each entry
in the table starting at location 0. The first matching entry’s location address L is the winning address that is driven as part of the
SRAM address on the SADR[23:0] lines (see “SRAM Addressing” on page 86).
The Search command is a pipelined operation and executes a Search at one-fourth the rate of the frequency of CLK2X for 288-
bit searches in ×288-configured tables. The latency of SADR, CE_L, ALE_L, WE_L, SSV, and SSF from the 288-bit Search
command (measured in CLK cycles) from the CLK2X cycle that contains the C and D cycles is shown in Table 10-26.
Table 10-26. Search Latency from Instruction to SRAM Access Cycle
Search latency from command to SRAM access cycle is 6 for a single device in the table and TLSZ = 10. In addition, SSV and
SSF shift further to the right for different values of HLAT, as specified in Table 10-27.
Table 10-27. Shift of SSF and SSV from SADR
Document #: 38-02035 Rev. *E
Notes:
26. For 288-bit searches, the host ASIC must supply four distinct 72-bit data words on DQ[71:0] during cycles A, B, C, and D. The GMR index in cycle A selects
27. The matching address is always going to be location 0 in a four-entry page for 288-bit search (two LSBs of the matching index will be 00).
• Cycle D: The host ASIC continues to drive CMDV HIGH and to apply Search command code (10) on CMD[1:0]. CMD[8:6]
signals must be driven with the index of the SSR that will be used for storing the address of the matching entry and the hit flag
(see page 14 for a description of SSR[0:7]). The DQ[71:0] is driven with the 72-bit data ([71:0]) to be compared to all locations 3
in the four 72-bits-word pages. CMD[5:2] is ignored because the Learn instruction is not supported for ×288 tables.
a pair of GMRs in each of the fifteen devices that apply to DQ data in cycles A and B. The GMR index in cycle C selects a pair of GMRs in each of the fifteen
devices that apply to DQ data in cycles C and D.
Number of Devices
1–15 (TLSZ = 10)
1–8 (TLSZ = 01)
HLAT
000
001
010
100
101
011
110
111
1,966,076
Location
address
GMR
12
L
0
4
8
K
287
Figure 10-61. ×288 Table with Fifteen Devices
287
A
0
CFG = 1010101010101010
(288-bit configuration)
Max Table Size
128K × 288 bits
480K × 288 bits
B
1
C
2
Number of CLK Cycles
[27]
D
3
0
1
2
3
4
5
6
7
0
0
(First matching entry)
Latency in CLK Cycles
Must be same in each of the 15
5
6
CYNSE70256
devices
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