CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 87

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

12.2
The following explains the SRAM Read operation completed through a table of up to four devices using the following parameter:
TLSZ = 01. Figure 12-1 diagrams a block of four devices. The following assumes that SRAM access is successfully achieved
through CYNSE70256 device number 0. Figure 12-2 and Figure 12-3 show timing diagrams for device number 0 and device
number 3, respectively.
At the end of cycle 7, the selected device floats ACK in a three-state condition. A new command can begin.
Document #: 38-02035 Rev. *E
• Cycle 1A: The host ASIC applies the Read instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address, with
• Cycle 1B: The host ASIC continues to apply the Read instruction on CMD[1:0], using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC floats DQ[71:0] to a three-state condition.
• Cycle 3: The host ASIC keeps DQ[71:0] in a three-state condition.
• Cycle 4: The selected device starts to drive DQ[71:0].
• Cycle 5: The selected device continues to drive DQ[71:0] and drives ACK from High-Z to LOW.
• Cycle 6: The selected device drives the Read address on SADR[23:0], and drives ACK HIGH, CE_L LOW, WE_L HIGH, and
• Cycle 7: The selected device drives CE_L , ALE_L, WE_L, and the DQ bus in a three-state condition. It continues to drive
DQ[20:19] set to 10, to select the SRAM address. The host ASIC selects the device for which ID[4:0] matches the DQ[25:21]
lines. During this cycle the host ASIC also supplies SADR[23:21] on CMD[8:6].
address, with DQ[20:19] set to 10, to select the SRAM address.
ALE_L LOW.
ACK LOW.
CMDV
CMD[10:0]
SSF, SSV
DQ[71:0]
SRAM Read with a Table of up to Four Devices
Figure 12-1. Hardware Diagram of a Block of Four Devices
BHI[2:0]
BHI[2:0]
BHI[2:0]
BHI[2:0]
CYNSE70256 #2
CYNSE70256 #3
CYNSE70256 #0
CYNSE70256 #1
0
0
0
0
LHO[1]
LHO[1]
1
1
1
1
LHO[1]
2
2
2
2
LHI
LHI
LHI
LHI
LHO[1]
LHO[0]
3
3
3
3
LHO[0]
4
4
4
4
LHO[0]
5
5
5
5
LHO[0]
6
6
6
6
CYNSE70256
BHO[0]
BHO[1]
BHO[2]
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SRAM