CYNSE70256-66BHC Cypress Semiconductor Corp, CYNSE70256-66BHC Datasheet - Page 91

• Manufacturer Part Number: CYNSE70256-66BHC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70256-66BHC

• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

At the end of cycle 3, a new command can begin. Write is a pipelined operation, but the Write cycle appears at the SRAM bus
with the same latency as that of a Search instruction, as measured from the second cycle of the Write command.
Note:
Document #: 38-02035 Rev. *E
34. CMD[2] must be set to 0 for SRAM Write because burst Writes into the SRAM are not supported.
• Cycle 1A: The host ASIC applies the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the address with
• Cycle 1B: The host ASIC continues to apply the Write instruction on CMD[1:0] using CMDV = 1. The DQ bus supplies the
• Cycle 2: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device.
• Cycle 3: The host ASIC continues to drive DQ[71:0]. The data in this cycle is not used by the CYNSE70256 device.
DQ[20:19] set to 10 to select the SRAM address. The host ASIC selects the device for which the ID[4:0] matches the DQ[25:21]
lines. The host ASIC also supplies SADR[23:21] on CMD[8:6] in this cycle.
address with DQ[20:19] set to 10 to select the SRAM address.
DQ[71:0]
CMDV
CMD[10:0]
SSF, SSV
SADR[23:0]
CMD[10:2]
CMD[1:0]
CLK2X
PHS_L
ALE_L
CMDV
WE_L
OE_L
CE_L
Figure 12-8. SRAM Write Through Device Number 0 in a Block of Four Devices
ACK
SSV
SSF
TLSZ = 01, HLAT = XXX, LRAM = 0, LDEV = 0
DQ
Figure 12-7. Hardware Diagram of a Block of Four Devices
BHI[2:0]
z
z
z
z
z
z
z
z
BHI[2:0]
BHI[2:0]
BHI[2:0]
Address
cycle
Write
1
A B
01
CYNSE70256 #0
CYNSE70256 #1
CYNSE70256 #2
CYNSE70256 #3
cycle
2
x
cycle
3
x
cycle
4
[34]
0
0
0
0
LHO[1]
cycle
LHO[1]
5
1
1
1
1
LHO[1]
cycle
6
2
2
2
2
[34]
LHI
LHI
LHI
LHI
LHO[1]
cycle
Address
LHO[0]
3
3
3
3
7
LHO[0]
0
0
0
4
4
4
cycle
4
LHO[0]
8
z
z
z
z
5
5
5
5
cycle
LHO[0]
9
z
6
6
6
6
cycle
10
CYNSE70256
SRAM
Page 91 of 109
BHO[0]
BHO[1]
BHO[2]