B69000 Asiliant Technologies, B69000 Datasheet - Page 34

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

2-10
Flat Panel Display Interface (continued)
Notes:
To accommodate a wide variety of panel types, the graphics controller has been designed to output its data
in any of a number of formats. These formats include different data widths for the colors belonging to each
pixel, and the ability to accommodate different pixel data transfer timing requirements.
For STN-DD panels, pins P0 through P35 are organized into groups corresponding to the upper and lower
parts of the panel. The names of the signals for the upper and lower parts follow a naming convention of
Uxx and Lxx, respectively.
For panels that require a pair of adjacent pixels be sent with every shift clock, pins P0 through P35 are
organized into groups corresponding to the first and second (from right to left) pixels of each pair of pixels
being sent. The names of the signals for the first and second pixels of each such pair follow a naming
convention of Fxx and Sxx, respectively.
Panels that transfer data on both edges of SHFCLK are also supported. See the description for register
FR12 for more details.
&+,36
BGA mBGA
PIN
U6
W4
W5
V6
Y5
Y4
V5
PIN
M6
P5
N5
T4
R4
L7
T3
69000 Databook
Pin Name
SHFCLK
FLM
LP (CL1)(DE)
(BLANK#)
M (DE)
(BLANK#)
ENAVDD
ENAVEE
(ENABKL)
ENABKL
Type
OUT
OUT
OUT
OUT
I/O
I/O
I/O
Subject to Change Without Notice
Active
High
High
High
High
High
High
High
Pin Descriptions
Powered Description
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
IOVCC
& GND
Shift Clock. Pixel clock for flat panel data.
First Line Marker. Flat Panel equivalent of VSYNC.
Latch Pulse. Flat Panel equivalent of HSYNC. May
also be configured as Displa Enable (DE) or
BLANK#. Some panels use the signal name of CL1.
M signal for panel AC drive control (may also be
called ACDCLK). May also be configured as
BLANK# or as Display Enable (DE) for TFT Panels.
Power sequencing control for panel driver
electronics voltage VDD.
Power sequencing control for panel bias voltage
VEE. May also be configured as ENABKL.
Power sequencing control for enabling the backlight.
Revision 1.3 8/31/98