B69000 Asiliant Technologies, B69000 Datasheet - Page 177

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

14-10
2
1
0
Note:
&+,36
Planar to Non-Planar Address Translation Enable
This bit provides a single-bit switch that can be used to alter the manner in which the frame buffer
memory appears from the perspective of the host bus to be organized so that it looks as though the
bits for each pixel are organized sequentially rather than in planes, even though it may well still be
organized in planes. This is done through a hardware-based address translation scheme. The
result is intended to be very similar to setting the frame buffer memory to chain-4 mode using the
graphics controller registers.
This switch is meant to be turned on occasionally as a convenience to programmers when the
graphics controller is being used in standard VGA modes, in order to allow a given drawing
operation or frame buffer save or restore operation to be carried out more easily. Altering this bit
has no effect on the settings in the graphics controller registers (the GRxx series registers) that are
normally used to specify the way in which the frame buffer memory is organized. It is
recommended, however, that bits 3 and 2 of the Miscellaneous Register (GR06) be set so that the
frame buffer memory is accessible using the A0000-AFFFF memory space during the time that this
feature is used.
0: Disables address translation in support of packed mode. This is the default after reset.
1: Enables address translation in support of packed mode.
Frame Buffer Linear Mapping Enable
0: Disables the linear mapping of the frame buffer.
1: Enables the linear mapping of the frame buffer.
Frame Buffer Page Mapping Enable
0: Disables the mapping of the frame buffer in 64KB pages into the A0000h-AFFFFh memory
address space.
1: Enables the mapping of the frame buffer in 64KB pages into the A0000h-AFFFFh memory
address space.
The selection of which 64KB page is to be mapped into memory addresses A0000h-AFFFFh is
made using bits 6-0 of the Frame Buffer Page Selector Register (XR0E).
69000 Databook
Subject to Change Without Notice
Extension Registers
Revision 1.3 8/31/98