B69000 Asiliant Technologies, B69000 Datasheet - Page 151

• Manufacturer Part Number: B69000
• Manufacturer: Asiliant Technologies

Specifications of B69000

• Lead Free Status / Rohs Status: Supplier Unconfirmed

11-8
3
2
1-0
&+,36
Read Mode
Reserved
Write Mode
69000 Databook
0: During a CPU read from the frame buffer, the value returned to the CPU is data from the
memory plane selected by bits 1 and 0 of the Read Plane Select Register (GR04).
1: During a CPU read from the frame buffer, all 8 bits of the byte in each of the 4 memory
planes corresponding to the address from which a CPU read access is being performed are
compared to the corresponding bits in this register (if the corresponding bit in the Color
Don’t Care Register (GR07) is set to 1). The value that the CPU receives from the read
access is an 8-bit value that shows the result of this comparison, wherein value of 1 in a
given bit position indicates that all of the corresponding bits in the bytes across all 4 of the
memory planes that were included in the comparison had the same value as their memory
plane’s respective bits in this register.
0, 0: Write Mode 0 -- During a CPU write to the frame buffer, the addressed byte in each
of the 4 memory planes is written with the CPU write data after it has been rotated by the
number of counts specified in the Data Rotate Register (GR03). If, however, the bit(s) in
the Enable Set/Reset Register (GR01) corresponding to one or more of the memory planes
is set to 1, then those memory planes will be written to with the data stored in the
corresponding bits in the Set/Reset Register (GR00).
0, 1: Write Mode 1 -- During a CPU write to the frame buffer, the addressed byte in each
of the 4 memory planes is written to with the data stored in the memory read latches (the
memory read latches stores an unaltered copy of the data last read from any location in the
frame buffer).
1, 0: Write Mode 2 -- During a CPU write to the frame buffer, the least significant 4 data
bits of the CPU write data are treated as the color value for the pixels in the addressed byte
in all 4 memory planes. The 8 bits of the Bit Mask Register (GR08) are used to selectively
enable or disable the ability to write to the corresponding bit in each of the 4 memory planes
that correspond to a given pixel. A setting of 0 in a bit in the Bit Mask Register at a given
bit position causes the bits in the corresponding bit positions in the addressed byte in all 4
memory planes to be written with value of their counterparts in the memory read latches.
A setting of 1 in a Bit Mask Register at a given bit position causes the bits in the
corresponding bit positions in the addressed byte in all 4 memory planes to be written with
the 4 bits taken from the CPU write data to thereby cause the pixel corresponding to these
bits to be set to the color value.
1, 1: Write Mode 3 -- During a CPU write to the frame buffer, the CPU write data is logically
ANDed with the contents of the Bit Mask Register (GR08). The result of this ANDing is
treated as the bit mask used in writing the contents of the Set/Reset Register (GR00) are
written to addressed byte in all 4 memory planes.
Subject to Change Without Notice
Graphics Controller Registers
Revision 1.3 8/31/98