DSP56002FC66 Freescale Semiconductor, DSP56002FC66 Datasheet - Page 36

• Manufacturer Part Number: DSP56002FC66
• Manufacturer: Freescale Semiconductor

Specifications of DSP56002FC66

• Device Core Size: 24b
• Architecture: Harvard
• Format: Fixed Point
• Clock Freq (max): 66MHz
• Mips: 33
• Device Input Clock Speed: 66MHz
• Ram Size: 3KB
• Program Memory Size: 1.5KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Specifications
RESET, Stop, Mode Select, and Interrupt Timing
2-10
Notes:
Num
28
A0-A15,
CKOUT
RESET
DS, PS
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)
A0–A15
RESET
Delay from Level Sensitive IRQA Assertion to Fetch of First
Interrupt Instruction (when exiting ‘Stop’)
X/Y
1.
2.
3.
•
•
•
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases:
• after power-on reset, and
• when recovering from Stop mode.
During this stabilization period, T
varies, a delay of 75,000 T
programs.
Circuit stabilization delay is required during reset when using an external clock in two cases:
• after power-on reset, and
• when recovering from Stop mode.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through
22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-
triggered mode is recommended when using fast interrupt. Long interrupts are recommended when
using Level-sensitive mode.
Internal Crystal Oscillator Clock, OMR bit 6 = 0
Stable External Clock, OMR bit 6 = 1
Stable External Clock, PCTL bit 17= 1
9
12
Characteristics
Figure 2-5 Synchronous Reset Timing
Freescale Semiconductor, Inc.
For More Information On This Product,
C
is typically allowed to assure that the oscillator is stable before executing
Figure 2-4 Reset Timing
DSP56002/D, Rev. 3
C
Go to: www.freescale.com
, T
H,
10
and T
1
L
13
will not be constant. Since this stabilization period
65548T
20T
13T
Min
C
C
C
11
First Fetch
Max
V
MOTOROLA
—
—
—
IHR
AA0356
AA0357
Unit
ns
ns
ns