DSP56002FC66 Freescale Semiconductor, DSP56002FC66 Datasheet - Page 35

• Manufacturer Part Number: DSP56002FC66
• Manufacturer: Freescale Semiconductor

Specifications of DSP56002FC66

• Device Core Size: 24b
• Architecture: Harvard
• Format: Fixed Point
• Clock Freq (max): 66MHz
• Mips: 33
• Device Input Clock Speed: 66MHz
• Ram Size: 3KB
• Program Memory Size: 1.5KB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

MOTOROLA
Num
16a Minimum Edge-Triggered Interrupt Request Deassertion
17
18
19
20
21
22
23
24
25
26
27
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)
Width
Delay from IRQA, IRQB, NMI Assertion to External Memory
Access Address Out Valid
Delay from IRQA, IRQB, NMI Assertion to General Purpose
Transfer Output Valid caused by First Interrupt Instruction
Execution
Delay from Address Output Valid caused by First Interrupt
Instruction Execute to Interrupt Request
Deassertion for Level Sensitive Fast Interrupts
Delay from RD Assertion to Interrupt Request
Deassertion for Level Sensitive Fast Interrupts
Delay from WR Assertion to Interrupt Request Deassertion
for Level Sensitive Fast Interrupts
Delay from General-Purpose Output Valid to Interrupt
Request Deassertion for Level Sensitive Fast Interrupts
—If Second Interrupt Instruction is:
Synchronous Interrupt Setup Time from IRQA, IRQB, NMI
Assertion to the second CKOUT transition
Synchronous Interrupt Delay Time from the second CKOUT
transition to the First External Address Output Valid caused
by the First Instruction Fetch after coming out of Wait State
Duration for IRQA Assertion to Recover from Stop State
Delay from IRQA Assertion to Fetch of First Interrupt
Instruction (when exiting ‘Stop’)
Duration of Level Sensitive IRQA Assertion to ensure
interrupt service (when exiting ‘Stop’)
•
•
•
•
•
•
•
•
•
•
•
•
Caused by First Interrupt Instruction Fetch
Caused by First Interrupt Instruction Execution
WS = 0
WS > 0
Single Cycle
Two Cycles
Internal Crystal Oscillator Clock, OMR bit 6 = 0
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17 = 1
Internal Crystal Oscillator Clock, OMR bit 6 = 0
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17 = 1
Freescale Semiconductor, Inc.
For More Information On This Product,
Characteristics
Go to: www.freescale.com
1
DSP56002/D, Rev. 3
3
1
3
3
RESET, Stop, Mode Select, and Interrupt Timing
3
65534T
11T
13T
5T
9T
6T
65548T
20T
13T
Min
C
C
C
C
C
13
—
—
—
—
—
—
12
10
12
+ T
+ T
+ T
+ T
+ T
C
C
C
+ T
C
H
H
L
H
H
L
(T
(T
(T
13T
2T
2 T
C
C
C
T
2T
C
C
T
C
2T
C
+ T
Max
L –
C
+ T
WS) – 23
WS) – 21
WS) – 21
+ T
T
Specifications
—
—
—
—
—
—
—
—
—
—
—
+ T
C
C
– 21
31
L
+
L
H
L
– 31
+
+ 6
+
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2-9