SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 96

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.15.4
An immediate access cycle consists of one address phase and one data phase. A block transfer with address increment
enabled consists of several consecutive address/data phase couples. A block transfer with disabled address increment
consists of one address phase followed by several data phases. The AS_ALE signal toggles only for a new address
phase.The single bytes or words are assembled/disassembled to/from Dwords. This includes byte lane swapping since
8-bit devices use for data transfer AD7 to AD0 only, (AD15 to AD8 are used in address phase too, since all 16 AD lines
are used for addressing.)
2004 Aug 25
handbook, full pagewidth
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
F
UNCTIONAL DESCRIPTION
AS_ALE
DEBI
FIFO
block length
DMA address
TRANSFER CONTROL AND DATA ASSEMBLING/DISASSEMBLING
UDS_WRN
target bus control signals
32
32
Motorola style
LDS_RDN
immed.
Intel style
data
DEBI_AD
DTACK_RDY
32
Fig.29 DEBI interface.
DATA MUX AND CYCLE CONTROL
RWN_SBHE
command words
DEBI_CONFIG
96
32
(XIRQ)
GPIO3
32
DEBI_COMMAND
adress/data lines
AD16 (15 to 0)
multiplexed
8
8
status
SAA7146A
16/8-bit
slave
MHB062
Product specification
SAA7146A