SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 77

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.11.2
All YUV formats are based on CCIR coding:
Luminance Y in straight binary:
Colour difference signals UV in offset binary:
The following formats use video FIFO 3, DMA Channel 3 and are packed formats.
Table 65 YUV 4 : 2 : 2 formats
7.11.2.1
7.12
7.12.1
The initial settings of the Dual D1 interface contains all control bits of the scaler part which do not change during a cyclic
processing of the video path. These control bits must be initialized at the beginning of the processing. The different
upload conditions of the video path depend on these control bits. Changing these bits during the active processing can
cause a valid UPLOAD.
2004 Aug 25
Y
Black: Y = 16 of 256 linear coding
White: Y = 235 of 256 linear coding.
No colour: U = V = 128 of 256 steps
Full colour: U = V = 128 112 steps.
YUV 4 : 2 : 2 U and V sampled co-sided with first Y sample (of 2 samples in-line). Byte phase of the first sample each
line is defined by bit 0 and bit 1 of DMA base address.
1
Y8; uses only the Y portion of the data stream and packs four bytes in one Dword
YUV 4 : 2 : 2; packs two pixel into one Dword, the order is Y
1-bit format; the Y1 format is a 1-bit format which packs 32 times the most significant bit of luminance (Y) into one
Dword, the first bit is bit 31 of the Dword
2-bit format; the Y2 format is a 2-bit format which packs 16 times the two most significant bits of luminance (Y) into
one Dword, the first bit is bit 31 of the Dword.
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
BIT 31 TO BIT 24
Scaler register
B
I
NITIAL SETTING OF DUAL
INARY RATIO SCALER OUTPUT FORMATS
VBI data formats
V
0
D1
BIT 23 TO BIT 16
INTERFACE
PACKING WITHIN 32-BIT Dword
77
Y
0
1
, V
BIT 15 TO BIT 8
0
, Y
0
, U
0
U
0
BIT 7 TO BIT 0
Product specification
SAA7146A