SAA7146AH NXP Semiconductors, SAA7146AH Datasheet - Page 39

• Manufacturer Part Number: SAA7146AH
• Manufacturer: NXP Semiconductors

Specifications of SAA7146AH

• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.5
7.5.1
In order to control the SAA7146A, the status information is collected and stored in two status registers: Primary Status
Register (PSR) and Secondary Status Register (SSR). These two registers follow a hierarchical approach because the
PSR contains summed up information from the SSR. Interrupts can only be generated from the PSR and are enabled
via the Interrupt Enable Register (IER). If an interrupt condition occurs and the interrupt is enabled, the corresponding
bit in the Interrupt Status Register (ISR) is set. These bits can be cleared by writing a logic 1.
Both status registers are read only. Writing a logic 1 into any of the PSR bits causes the corresponding interrupt to be
generated if enabled. Writing a logic 0 has no effect.
Table 38 Primary status register
2004 Aug 25
110
OFFSET
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
(HEX)
Status and interrupts
G
ENERAL
PPEF
PABO
PPED
RPS_I1
RPS_I0
RPS_late1
RPS_late0
RPS_E1
RPS_E0
RPS_TO1
NAME
31
30
29
28
27
26
25
24
23
22
BIT
R
R
R
R
R
R
R
R
R
R
TYPE
PCI Parity Error: this bit is set when a PCI Parity Error occurs
during any transfer other than ‘real time video data’. The bit in
the ISR is set on the rising edge of this status bit.
PCI Access Error: this bit is set when the PCI interface starts
an access, and has either a target or master abort. The bit in
the ISR is set on the rising edge of this status bit.
PCI Parity Errors on ‘real time Data’: this bit is set when a
parity error has occurred since the last Vsync or under RPS
since the last wait.
Interrupt issued by RPS command from Task 1.
Interrupt issued by RPS command from Task 0.
RPS Task 1 late: this is set by the CHECK_LATE command.
This bit is reset by starting a new RPS Task 1.
RPS Task 0 late: this is set by the CHECK_LATE command.
This bit is reset by starting a new RPS Task 0.
RPS_Error Task 1: this bit reflects the status of the RPS
error bits for Task 1 in the secondary status register
(see Table 39). This bit is reset by starting a new RPS Task 1.
RPS_Error Task 0: this bit reflects the status of the RPS
error bits for Task 0 in the secondary status register
(see Table 39). This bit is reset by starting a new RPS Task 0.
RPS time out error in Task 1: this bit is set when the RPS
Task 1 stays longer than expected in the WAIT state. This bit
is reset by starting a new RPS Task 1.
39
DESCRIPTION
Product specification
SAA7146A
ISR [31]
ISR [30]
RESET