MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 240

• Manufacturer Part Number: MC68EC040RC25
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040RC25

• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 179
• Package Type: PGA
• Lead Free Status / Rohs Status: Supplier Unconfirmed

back data (WB3D, WB2D, and WB1D). WB3A and WB3D correspond to the temporary
holding register in the integer unit (WB3). WB2A and WB2D correspond to the temporary
holding register in the data memory unit (WB2) prior to address translation. WB1A and
WB1D correspond to the temporary holding register in the bus controller (WB1), which
determines the external address and data bus bit patterns. Refer to Section 2 Integer
Unit for details on the operation of the integer unit pipeline.
The write-back data in WB3D and WB2D is register aligned with byte and word data
contained in the least significant byte and word, respectively, of the field. Write-back data
in WB1D is memory aligned and resides in the byte positions corresponding to the data
bus lanes used in writing each byte to memory. Table 8-5 lists the data alignment for each
combination of data format and A1 and A0.
8.4.6.6 PUSH DATA. The push data field contains an image of the cache line that needs
to be pushed to memory.
8.4.6.7 ACCESS ERROR STACK FRAME RETURN FROM EXCEPTION. For the access
error stack frame (format $7), the processor restores the SR and PC values from the stack
and checks the four continuation status bits in the SSW on the stack. If these bits are not
set, the processor increments the active supervisor stack pointer by 30 words and
resumes normal instruction execution. If the MOVEM continuation bit is set, the processor
restores the calculated effective address from the stack frame, increments the active
supervisor stack pointer by 30 words, and restarts the MOVEM instruction at a point after
the effective address calculation. All operand accesses for the MOVEM that occurred
before the faulted access are repeated. If a continuation bit is set for a pending trace,
unimplemented floating-point instruction, or floating-point post-instruction exception, the
processor restores the calculated effective address from the stack frame, increments the
active supervisor stack pointer by 30 words, and immediately begins exception processing
MOTOROLA
NOTE: For a line transfer fault, the four long words of data in PD3–
Byte
Word
Long Word
Data Format
Freescale Semiconductor, Inc.
PD0 are already aligned with memory. Bits 31–0 of each field
correspond to bits 31–0 of the memory location to be written to,
regardless of the value of the address bits A1 and A0 for the
write-back address.
Table 8-5. Write-Back Data Alignment
For More Information On This Product,
A1
Address
0
0
1
1
0
0
1
1
0
0
1
1
Go to: www.freescale.com
M68040 USER’S MANUAL
A0
0
1
0
1
0
1
0
1
0
1
0
1
23–0, 31–24
15–0, 31–16
7–0, 31–24
7–0, 31–8
WB1D
31–24
23–16
31–16
15–8
23–8
15–0
31–0
7–0
Data Alignment
WB2D, WB3D
15–0
15–0
15–0
15–0
31–0
31–0
31–0
31–0
7–0
7–0
7–0
7–0
8- 27