MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 213

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MC68EC040RC25

Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC040RC25

Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed

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Case 1
Case 2
MOTOROLA
If DLE is negated and meets setup time specification #35 to the rising edge of BCLK
when the bus read is terminated, latch A is transparent, and the read data must meet
setup and hold time specifications #36 and #37 to the rising edge of BCLK. Read timing
is similar to normal timing for this case.
If DLE is asserted, the data bus levels are latched and held internally. D31–D0 must
meet setup and hold time specifications #32 and #33 to the falling edge of DLE, and can
transition to a new level once DLE is asserted. D31–D0 must still meet setup time
specification #36 to BCLK, but not hold time specification #37, since the data is
internally held valid as long as DLE remains asserted low.
D0–D31 IN
(READ)
BCLK
DLE
TA
Figure 7-48. DLE versus Normal Data Read Timing
Freescale Semiconductor, Inc.
36
For More Information On This Product,
35
D0–D31 IN
CASE 1
(READ)
BCLK
Go to: www.freescale.com
M68040 USER’S MANUAL
TA
37
DLE MODE DATA BUS TIMING
NORMAL DATA BUS TIMING
15
32
16
31
CASE 2
36
33
34
7- 71

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