MC68EC040RC25 Freescale Semiconductor, MC68EC040RC25 Datasheet - Page 204

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MC68EC040RC25

Manufacturer Part Number
MC68EC040RC25
Description
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MC68EC040RC25

Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
25MHz
Instruction Set Architecture
RISC
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
179
Package Type
PGA
Lead Free Status / Rohs Status
Supplier Unconfirmed

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illustrated, which results in a memory access having the equivalent of two wait states.
Variations in the timing required by snooping logic to access the caches can delay the
negation of MI by up to two additional clocks. External logic must ensure that the
termination signals negate at all rising BCLK edges in which MI is asserted. Otherwise, if
one of the termination signals is asserted, either the M68040 ignores all termination
signals, reading them as negated, or the M68040 exhibits improper operation.
7-62
SIZ1, SIZ0
*
SC1–SC0
TT1, TT0
AM_BR
AM_BG
AM indicates the alternate bus master.
D31–D0
A31–A0
Figure 7-41. Snoop Access with Memory Response
BCLK
R/W
BR
BG
TS
TA
BB
MI
*
*
Undefined
Freescale Semiconductor, Inc.
C1
For More Information On This Product,
C2
M68040 USER’S MANUAL
Go to: www.freescale.com
C3
ALTERNATE
MASTER
C4
C5
C6
PROCESSOR
MOTOROLA

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