GC80960RD66 Intel, GC80960RD66 Datasheet - Page 25

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Table 7.
Datasheet
PCI Signal Descriptions (Sheet 2 of 3)
NOTE:
1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, Revision
S_DEVSEL#
S_C/BE3:0#
S_FRAME#
S_GNT5:1#
S_GNT0#/
S_REQ0#/
S_AD31:0
S_LOCK#
S_PERR#
P_STOP#
P_TRDY#
2.1 for a more complete definition.
S_IDSEL
S_IRDY#
S_REQ#
S_GNT#
S_RST#
S_PAR
Name
Type
R(Q)
R(Q)
R(Z)
R(Z)
R(0)
R(0)
R(Z)
R(Z)
R(Z)
S(L)
R(Z)
R(Z)
R(0)
R(Z)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
I
I
PRIMARY PCI BUS STOP indicates that the current target is requesting the
master to stop the current transaction on the primary PCI bus.
PRIMARY PCI BUS TARGET READY indicates the target agent's (selected
device's) ability to complete the current data phase of the transaction.
SECONDARY PCI ADDRESS/DATA is the secondary multiplexed PCI
address and data bus. A bus transaction consists of an address phase
followed by one or more data phases.
SECONDARY PCI BUS COMMAND and BYTE ENABLE signals are
multiplexed on the same PCI signals. During an address phase,
S_C/BE3:0# define the bus command. During a data phase, S_C/BE3:0#
are used as byte enables.
SECONDARY PCI BUS DEVICE SELECT is driven by a target agent that
has successfully decoded the address. As an input, it indicates whether or
not an agent has been selected.
SECONDARY PCI BUS CYCLE FRAME is asserted to indicate the
beginning and duration of an access on the Secondary PCI bus.
SECONDARY PCI BUS GRANT0 is a grant signal sent to device 0 on the
secondary PCI bus when the internal Secondary PCI Bus Arbiter is enabled.
SECONDARY PCI BUS REQUEST is the request signal for the 80960RX
when the arbiter is disabled.
SECONDARY PCI BUS GRANT are grant signals sent to devices 1-5 on the
secondary PCI bus.
SECONDARY PCI BUS INITIALIZATION DEVICE SELECT selects the
80960RX during a Configuration Read or Write command on the secondary
PCI bus.
SECONDARY PCI BUS INITIATOR READY indicates the initiating agent's
(bus master's) ability to complete the current data phase of the transaction.
SECONDARY PCI BUS LOCK indicates the need to perform an atomic
operation on the secondary PCI bus.
SECONDARY PCI BUS PARITY. This signal ensures even parity across
S_AD31:0 and S_C/BE3:0. All PCI devices must provide a parity signal.
SECONDARY PCI BUS PARITY ERROR is used for reporting data parity
errors during all PCI transactions except a special cycle.
SECONDARY PCI BUS REQUEST0 is a request signal from device 0 on the
secondary PCI bus when the internal Secondary PCI Bus Arbiter is enabled.
SECONDARY PCI BUS GRANT is the grant signal for the 80960RX when
the arbiter is disabled.
SECONDARY PCI BUS RESET is an output based on P_RST#. It brings
PCI-specific registers, sequencers, and signals to a consistent state. When
P_RST# is asserted, it causes S_RST# to assert, and:
S_RST# may be asynchronous to S_CLK when asserted or deasserted.
• PCI output signals are driven to a known consistent state.
• PCI bus interface output signals are three-stated.
• open drain signals such as S_SERR# are floated.
Intel
®
Description
i960
®
RX I/O Processor at 3.3 Volts
1
Package Information
25