GC80960RD66 Intel, GC80960RD66 Datasheet
GC80960RD66
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... Two Channels Dedicated to Primary PCI Bus — One Channel Dedicated to Secondary PCI Bus I/O APIC Bus Interface Unit — Multiprocessor Interrupt Management for Intel Architecture CPUs (Pentium ® and Pentium Pro Processors) — Dynamic Interrupt Distribution — Multiple I/O Subsystem Support ...
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... Information in this document is provided in connection with Intel property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...
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... C Bus Interface Unit ............................................................................................11 2.1.7.1 I/O APIC Bus Interface Unit ................................................................... 11 2.1.7.2 Secondary PCI Arbitration Unit .............................................................. 11 ® ® 2.2 Intel i960 Core Features (Intel 2.2.1 Burst Bus ...............................................................................................................13 2.2.2 Timer Unit .............................................................................................................. 13 2.2.3 Priority Interrupt Controller.....................................................................................13 2.2.4 Faults and Debugging............................................................................................14 2.2.5 On-Chip Cache and Data RAM ............................................................................. 14 2 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Contents 4.4.4 APIC Bus Interface Signal Timings........................................................................ 53 2 4.4 Interface Signal Timings .................................................................................. 54 4.5 AC Test Conditions............................................................................................................. 55 4.6 AC Timing Waveforms........................................................................................................ 55 4.7 Memory Controller Output Timing Waveforms ................................................................... 59 5.0 BUS FUNCTIONAL WAVEFORMS.............................................................................................. 66 6.0 DEVICE IDENTIFICATION ON RESET ........................................................................................ 75 4 Datasheet ...
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... Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus ................................................................ 71 32 HOLD/HOLDA Waveform For Bus Arbitration ............................................................................ 72 33 80960 Core Cold Reset Waveform............................................................................................. 73 34 80960 Local Bus Warm Reset Waveform................................................................................... 74 Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts Contents 5 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Contents Tables 1 Related Documentation ................................................................................................................ 8 2 80960RX Instruction Set............................................................................................................. 16 3 Signal Type Definition................................................................................................................. 17 4 Signal Descriptions ..................................................................................................................... 18 5 Power Requirement, Processor Control and Test Signal Descriptions ...................................... 22 6 Interrupt Unit Signal Descriptions ............................................................................................... 23 7 PCI Signal Descriptions .............................................................................................................. 24 8 Memory Controller Signal Descriptions ...
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... About This Document This is the data sheet for the low-power (3.3 V) versions of the Intel Processor family (80960RX), including: ® • Intel 80960RD 66/3.3 (80960RD) ® • Intel 80960RP 33/3.3 (80960RP) Throughout this document, these family members are referred to as the 80960RX when the information is common to both ...
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... Intel i960 RX I/O Processor at 3.3 Volts About This Document 1.3 Additional Information Sources Intel documentation is available from your local Intel Sales Representative or Intel Literature Sales. 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Table 1. Related Documentation ® i960 RP Microprocessor User’s Guide ® ...
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... Functional Overview As indicated in Figure 1 an intelligent I/O processor. Subsections following the figure briefly describe the main features; for detailed functional descriptions, refer to the Intel User’s Guide (272736). The PCI bus is an industry standard, high performance, low latency system bus that operates up to 132 Mbyte/s ...
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... The DMA Controller supports low-latency, high-throughput data transfers between PCI bus agents and 80960 local memory. Three separate DMA channels accommodate data transfers: two for primary PCI bus, one for the secondary PCI bus. The DMA Controller supports chaining and unaligned data transfers programmable only through the Intel ® i960 core processor ...
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... The Secondary PCI Arbitration Unit provides PCI arbitration for the secondary PCI bus. It includes a fairness algorithm with programmable priorities and six PCI Request and Grant signal pairs. This arbitration unit can also be disabled to allow for external arbitration. Datasheet ® Intel 2 C bus. The peripherals and microcontrollers for system management functions. ...
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... Controller 5 8-Set Local Register Cache 128 Global / Local Register File SRC1 SRC2 DST 3 Independent 32-Bit SRC1, SRC2, and DST Buses 12 ® Core Features (Intel Instruction Cache 4 Kbyte Two-Way Set Associative Instruction Sequencer Constants Control Execution Memory and Interface Multiply Divide Address ...
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... Interrupt vectors and interrupt handler routines can be reserved on-chip • Register frames for high-priority interrupt handlers can be cached on-chip • The interrupt stack can be placed in cacheable memory space Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts Functional Overview 13 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Functional Overview 2.2.4 Faults and Debugging The 80960RX employs a comprehensive fault model. The processor responds to faults by making implicit calls to a fault handling routine. Specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately. ...
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... The 80960RX provides a full set of addressing modes for C and assembly: • Two Absolute modes • Five Register Indirect modes • Index with displacement mode • IP with displacement mode Table 2 shows the available instructions. Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts Functional Overview 15 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Functional Overview Table 2. 80960RX Instruction Set Data Movement Load Store Move Conditional Select Load Address Comparison Compare Conditional Compare Compare and Increment Compare and Decrement Test Condition Code Check Bit Debug Modify Trace Controls ...
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... P(Q) Maintains previous state or continues valid output K (...) While the Secondary PCI Bus is being parked, the signal: K(Z) Floats K(Q) Maintains previous state or continues valid output Datasheet Intel Table 5 Table 6 defines signals associated with the Interrupt Unit. Table 8 defines Memory Controller signals. ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 4. Signal Descriptions (Sheet Name AD31:0 ADS# ALE BLAST# 18 Type ADDRESS / DATA BUS carries 32-bit physical addresses and 8-, 16- or 32-bit data to and from memory. During an address ( contain a physical word address (bits 0-1 indicate SIZE; see below). During ...
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... Intel i960 core processor; they do toggle for DMA and ATU cycles. They remain active through the last T DATA ENABLE indicates data transfer cycles during a bus access. DEN# is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 4. Signal Descriptions (Sheet Name LOCK#/ONCE# LRDYRCV# HOLD HOLDA RDYRCV# 20 Type BUS LOCK indicates that an atomic read-modify-write operation is in progress. The LOCK# output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. The processor does not grant HOLDA while asserting LOCK# ...
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... Table 4. Signal Descriptions (Sheet Name W/R# WIDTH/ HLTD0 WIDTH/ HLTD1/ RETRY Datasheet ® Intel Type WRITE/READ specifies during a O read latched on-chip and remains valid during T R(0) H( Read P( Write WIDTH denotes the physical memory attributes for a bus transaction in conjunction with WIDTH/HLTD1/RETRY: ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 5. Power Requirement, Processor Control and Test Signal Descriptions Name Type O R(0) FAIL# H(Q) L_RST STEST S(L) TCK I I TDI S(L) O R(Q) TDO H(Q) P(Q) I TMS S(L) I TRST# A(L) V – – ...
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... NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, Revision 2.1 for a more complete definition. Datasheet Intel NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur. I NMI# is the highest priority interrupt source and is level-detect. When NMI# is unused recommended that you connect SECONDARY PCI BUS INTERRUPT and deassertion is asynchronous to S_CLK ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 7. PCI Signal Descriptions (Sheet Name P_AD31:0 P_C/BE3:0# P_DEVSEL# P_FRAME# P_GNT# P_IDSEL P_INT[A:D]# P_IRDY# P_LOCK# P_PAR P_PERR# P_REQ# P_RST# P_SERR# NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, Revision 2 ...
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... PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, Revision 2.1 for a more complete definition. Datasheet ® Intel Type I/O PRIMARY PCI BUS STOP indicates that the current target is requesting the master to stop the current transaction on the primary PCI bus. ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 7. PCI Signal Descriptions (Sheet Name S_SERR# S_STOP# S_TRDY# S_REQ4:1# S_REQ5#/ S_ARB_EN NOTE: 1. PCI signal functions are summarized in this data sheet; refer to the PCI Local Bus Specification, Revision 2.1 for a more complete definition. ...
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... R(1) DWE1:0# H(Q) P(Q) R(1) LEAF1:0# H(Q) P(Q) Datasheet Intel COLUMN ADDRESS STROBE signals are used for DRAM accesses and are asserted when the MA11:0 signals contain a valid column address. CAS7:0# signals are asserted during refresh. Non-Interleaved Operation: CAS0# CAS4# BE0# , ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 8. Memory Controller Signal Descriptions (Sheet Name Type R(X) MA11:0 H(Q) P(Q) R(1) MWE3:0# H(Q) P(Q) R(1) RAS3:0# H(Q) P(Q) 28 MULTIPLEXED ADDRESS signals are multi-purpose depending on the device that is selected. O For memory banks 0 and 1, these signals output address bits A13:2. These address bits are incremented for each data transfer of a burst access ...
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... ICEVLD# O MSGFRM# O Datasheet Intel DMA DEMAND MODE ACKNOWLEDGE The DMA Controller asserts this signal to indicate (1) it can receive new data from an external device or (2) it has data to send to an external device. DMA DEMAND MODE REQUEST External devices use this signal to indicate (1) new data is ready for transfer to the DMA controller or (2) buffers are available to receive data from the DMA controller ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information 3.1.2 352-Lead HL-PBGA Package Figure 3. 352L HL-PBGA Package Diagram (Top and Side View) Ball A1 Corner 1.63 mm 0.63 ± 0.07 mm 1.54 ± 0.13 mm NOTES: 1. All dimensions and tolerances conform to ANSI Y14.5M 1982. ...
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... Figure 4. 352L HL-PBGA Package Diagram (Bottom View Datasheet ® Intel ® i960 RX I/O Processor at 3.3 Volts Package Information ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 ...
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... P_AD27 P_AD28 P_AD29 P_AD30 P_AD31 P_C/BE0# P_C/BE1# P_C/BE2# P_C/BE3# P_DEVSEL# P_FRAME# P_GNT# P_IDSEL P_INTA# P_INTB# P_INTC# P_INTD# P_IRDY# Datasheet ® Intel i960 Ball # Signal Ball # AE21 P_LOCK# AD17 AD21 P_PAR AD18 AE20 P_PERR# AF17 AF20 P_REQ# AE8 AD20 P_RST# AE7 AE19 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal S_RST# S_SERR# S_STOP# S_TRDY# SCL SDA STEST TCK TDI TDO TMS TRST ( Ball # Signal Ball # J25 V AF24 CC V25 V AF25 CC U25 V AF26 ...
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... Table 12. 352-Lead HL-PBGA Package — Signal Name Order (Sheet Signal W/R# WAIT# Datasheet ® Intel i960 Ball # Signal Ball # W4 WIDTH/HLTD0 AF5 Y23 WIDTH/HLTD1/RETRY AE5 C22 XINT4 XINT5# R3 ® RX I/O Processor at 3.3 Volts Package Information Signal Ball # XINT6# R1 XINT7 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal CCPLL3 A5 MA6 A6 V CCPLL2 A7 MA1 A8 AD30 A9 AD27 A10 AD24 A11 AD21 A12 AD18 A13 AD15 A14 AD12 A15 AD9 A16 ...
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... S_GNT0#/S_REQ# J1 MWE1# J2 MWE2# J3 MWE0 J23 V J24 S_AD30 J25 S_RST# J26 S_AD31 K1 DWE0# K2 DWE1# K3 MWE3 K23 V K24 S_AD27 K25 S_AD29 K26 S_AD28 Datasheet Intel Ball # Signal L1 CE1# L2 LEAF0 CE0 L23 V CC L24 S_AD24 L25 S_AD26 L26 S_AD25 M1 DALE0 M2 DALE1 SS M3 LEAF1 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal Y23 V Y24 S_AD10 Y25 S_AD12 Y26 S_AD11 AA1 ICEBRK# AA2 ICEMSG# AA3 ICEBUS7 AA4 V AA23 V AA24 S_C/BE0# AA25 S_AD9 AA26 ...
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... Table 13. 352-Lead HL-PBGA Pinout — Ballpad Number Order (Sheet Ball # Signal AF17 P_PERR# AF18 P_C/BE1# AF19 P_AD13 AF20 P_AD10 Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts Ball # Signal Ball # AF21 P_C/BE0# AF25 AF22 P_AD5 AF26 AF23 P_AD2 AF24 V CC ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information 3.2 Package Thermal Specifications The device is specified for operation when T 0° 95° C. Case temperature may be measured in any environment to determine whether the processor is within specified operating range. Measure the case temperature at the center of the top surface, opposite the ballpad ...
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... Thermocouple Attachment - With Heat Sink 3.2.1.3 Thermal Resistance The thermal resistance value for the case-to-ambient, cooling solution thermal performance. Datasheet ® ® Intel i960 Thermocouple 3.8 mm Diameter Hole CA RX I/O Processor at 3.3 Volts Package Information Heat Sink , is used as a measure of the ...
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... Intel i960 RX I/O Processor at 3.3 Volts Package Information 3.2.2 Thermal Analysis This thermal analysis is based on the following assumptions: • Power dissipation is a constant 5 W. • Maximum case temperature is 95° C. Table 14 lists the case-to-ambient thermal resistances of the 80960RP for different air flow rates with and without a heat sink ...
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... Company AAVID Thermalloy, Inc 80 Commercial Street Concord, NH 03301 USA info@aavid.com http://www.aavidthermalloy.com/atp/atp.html Parker Chromerics 77 Dragon Court Woburn, MA 01888 Datasheet ® Intel i960 Factory Phone # Representative Attention: Sales (603) 224-9988 (603) 223-1790 Attention: Sales (617) 935-4850 (617) 933-4318 ® RX I/O Processor at 3.3 Volts ...
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... SS CC Parameter Min 3.0 3 NOTICE: This data sheet contains information on products in the sampling and initial production phases of development. The specifications are subject to change without notice. Contact your local Intel representative before finalizing a design. Max Units Notes 3.6 V 5.25 V 33.33 MHz 95 °C ...
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... Table 17. V Specification for Dual Power Supply Requirements (3 DIFF Symbo Paramete CC5 CC V DIFF Difference Datasheet ® Intel ) DIFF CC5 outlines this requirement. specification. CC5 Figure CC5 pin does not exceed the maximum rating for this pin (±0.25 V) (±5%, 0.5 W) 100 plane ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 4.3 Targeted DC Specifications Table 18. DC Characteristics Symbol V Input Low Voltage IL Input High Voltage for all signals V IH1 except SCLK V Input High Voltage for SCLK IH2 V Output Low Voltage Processor signals OL1 ...
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... Active (Thermal) value is provided for your system thermal management. Typical I CC with V = 3.3 V and ambient temperature = 55 ° C. This parameter is characterized but not tested Active (Power modes) refers to the I CC ONCE mode with V Datasheet Intel Parameter 80960RP 33/3.3 80960RD 66/3.3 80960RP 33/3.3 80960RD 66/3.3 80960RP 33/3.3 80960RD 66/3.3 80960RP 33/3.3 80960RD 66/3.3 = 3.6 V and ambient temperature = 55 ° ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 4.4 Targeted AC Specifications Table 20. Input Clock Timings Symbol T S_CLK Frequency F T S_CLK Period C T S_CLK Period Stability CS T S_CLK High Time CH T S_CLK Low Time CL T S_CLK Rise Time CR T S_CLK Fall Time ...
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... S_CLK periods to guarantee recognition. 2. See Figure 12, “T 3. P_RST# may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at a particular clock edge. 4. Guaranteed by design. May not be 100% tested. Datasheet Intel Parameter and T Input Setup and Hold Waveform” on page IS IH ® ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 4.4.1 Relative Output Timings Table 23. Relative Output Timings Symbol T ALE Width LXL T Address Hold from ALE Inactive LXA T DT/R# Valid to DEN# Active DXD NOTES: 1. Guaranteed by design. May not be 100% tested. 2. See Figure 13, “ ...
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... T CAS7:0# Falling Edge Output Valid Delay - Write Cycles OV35 T MA11:0 Output Valid Delay - Row Address OV36 T MA11:0 Output Valid Delay - Column Address Read Cycles 0.5Tc +2 0.5Tc+10 OV37 Datasheet ® ® Intel i960 Description Min 0.5Tc maximium and V . CC3 SS Description maximium and V ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Table 27. BEDO DRAM Output Timings (Sheet MA11:0 Output Valid Delay - Column Address Write Cycles OV38 T DWE1:0# Rising and Falling Edge Output Valid Delay OV39 NOTES: 1. Signal generated on the rising edge of an internally generated 2XCLK which corresponds to the center of an S_CLK period ...
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... APIS1 T Input Hold from PICCLK — PICD1:0 APIH1 T Output Float Delay from PICCLK — PICD1:0 APOF Output Valid Delay from PICCLK — PICD1:0 (High to T APOVI Low) NOTE: 1. Not tested. Datasheet Intel Parameter Min Max maximium. CC5 Parameter ® ® i960 RX I/O Processor at 3 ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 2 4.4 Interface Signal Timings 2 Table 31 Interface Signal Timings Symbol F SCL Clock Frequency SCL T Bus Free Time Between STOP and START BUF Condition T Hold Time (repeated) START Condition HDSTA T SCL Clock Low Time ...
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... AC Test Conditions The AC Specifications in with the 50 pF load indicated in Figure 8. AC Test Load 4.6 AC Timing Waveforms Figure 9. S_CLK, TCLK Waveform T Figure 10. T Output Delay Waveform OV S_CLK Datasheet Intel Section 4.4, “Targeted AC Specifications” on page 48 Figure 8. Output Ball for all signals ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 11. T Output Float Waveform OF S_CLK Figure 12. T and T Input Setup and Hold Waveform IS IH S_CLK 56 1.5V 1. 1.5V 1.5V T IHX T ISX Valid 1.5V 1.5V Datasheet ...
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... Figure 13. T and T Relative Timings Waveform LXL LXA Figure 14. DT/R# and DEN# Timings Waveform S_CLK DT/R# DEN# Datasheet ® Intel T A 1.5V S_CLK T LXL ALE Valid 1.5V T LXA AD31:0 1.5V Valid T A 1.5V T OVX T DXD T ® i960 RX I/O Processor at 3.3 Volts ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions 2 Figure 15 Interface Signal Timings SDA T BUF SCL Stop Start 58 T LOW HDSTA HDDAT HIGH SUDAT SUSTA T T HDSTA SP T SUSTO Stop Repeated Start Datasheet ...
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... Memory Controller Output Timing Waveforms Figure 16. Fast Page-Mode Read Access, Non-Interleaved, 2,1,1,1 Wait State, 32-Bit 80960 Local Bus S_CLK AD31:0 MA11:0 ALE ADS# W/R# BLAST# DT/R# DEN# DWE0# RAS0# CAS3:0# LRDYRCV# RDYRCV# Datasheet ® Intel i960 DATA DATA ADDR In In COL ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 17. Fast Page-Mode Write Access, Non-Interleaved, 2,1,1,1 Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 MA11:0 ALE ADS# BE3:0# W/R# BLAST# DT/R# MWE0# DWE0# RAS0# CAS3:0# LRDYRCV# RDYRCV DATA DATA ADDR ...
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... Figure 18. FPM DRAM System Read Access, Interleaved, 2,0,0,0 Wait States S_CLK AD[31:0] RAS[n]# RAS[n+1#] MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0]# Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts ADDR COL ROW COL Electrical Specifictions ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 19. FPM DRAM System Write Access, Interleaved, 1,0,0,0 Wait States S_CLK AD[31:0] RAS[n]# RAS[n+1]# MA[11:0] DALE[0]# CAS[3:0]# LEAF[0]# DALE[1]# CAS[7:4]# LEAF[1]# DWE[1:0 DATA DATA DATA ADDR OUT OUT OUT COL ROW ...
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... Figure 20. EDO DRAM, Read Cycle S_CLK RAS# MA[11:0] CAS# AD[31:0] Figure 21. EDO DRAM, Write Cycle MA[11:0] AD[31:0] Datasheet Intel COL ROW COL D ADDR S_CLK RAS# COL COL COL COL ROW CAS ADDR OUT OUT ® ® i960 RX I/O Processor at 3.3 Volts ...
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... Intel i960 RX I/O Processor at 3.3 Volts Electrical Specifictions Figure 22. BEDO DRAM, Read Cycle S_CLK RAS# MA[11:0] CAS# AD[31:0] Figure 23. BEDO DRAM, Write Cycle MA[11:0] RITE CAS COL COL COL ROW ADDR S_CLK RAS# COL COL COL ROW COL D D AD[31:0] ...
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... Figure 24. 32-Bit Bus, SRAM Read Accesses with 0 Wait States MA[11:0] MWE[3:0]# AD[31:0] Figure 25. 32-Bit Bus, SRAM Write Accesses with 0 Wait States MWE[3:0]# Datasheet Intel S_CLK CE[1]# ADDR ADDR ADDR ADDR ADDR S_CLK CE[1]# ADDR ADDR ADDR ADDR MA[11: AD[31:0] ADDR OUT ...
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... Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS 5.0 BUS FUNCTIONAL WAVEFORMS Figure 26. Non-Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# ...
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... Figure 27. Burst Read and Write Transactions without Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Datasheet ® Intel i960 BUS FUNCTIONAL WAVEFORMS ADDR DATA DATA DATA ADDR ® RX I/O Processor at 3.3 Volts ...
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... Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 28. Burst Write Transactions with 2,1,1,1 Wait States, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV DATA DATA ADDR Out Out ...
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... Figure 29. Burst Read and Write Transactions without Wait States, 8-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE1/A1# BE0/A0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Datasheet ® Intel i960 BUS FUNCTIONAL WAVEFORMS ADDR DATA DATA DATA ADDR ® RX I/O Processor at 3.3 Volts ...
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... Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 30. Burst Read and Write Transactions with 1, 0 Wait States and Extra Tr State on Read, 16-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE1/A1# BE3# BE0# WIDTH1:0 D/C# W/R# BLAST# DT/R# ...
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... Figure 31. Bus Transactions Generated by Double Word Read Bus Request, Misaligned One Byte From Quad Word Boundary, 32-Bit 80960 Local Bus S_CLK AD31:0 ALE ADS# BE3:0# WIDTH1:0 D/C# W/R# BLAST# DT/R# DEN# LRDYRCV# RDYRCV# Datasheet ® Intel i960 Valid ® RX I/O Processor at 3.3 Volts ...
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... Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 32. HOLD/HOLDA Waveform For Bus Arbitration S_CLK Outputs: AD31:0, ALE, ADS#, BE3:0# D/C#/RSTMODE# LRDYRCV#, FAIL# WIDTH/HLTD1, WIDTH/HLTD1/RETRY, W/R#, DT/R#, DEN#, BLAST#, LOCK#/ONCE# HOLD HOLDA NOTE: HOLD is sampled on the rising edge of S_CLK. HOLDA is granted after the latency counter in the localbus arbiter expires ...
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... If the processor fails built-in self-test, it initiates one dummy load bus access. The load address indicates the point of self-test failure. Datasheet ® ® Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Idle (Note 2) Valid ...
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... Intel i960 RX I/O Processor at 3.3 Volts BUS FUNCTIONAL WAVEFORMS Figure 34. 80960 Local Bus Warm Reset Waveform S_CLK ADS#, BE3:0#,DEN#, BLAST#, D/C#/RST_MODE#, LRDYRCV#, WIDTH/HLTD0, WIDTH/HLTD1/RETRY, ALE, W/R#,DT/R# FAIL# AD31:0 HOLD HOLDA LOCK#/ONCE# STEST S_RST#, P_RST# L_RST# NOTE: Local bus warm reset occurs when Bit 5 in the Extended Bridge Control Register (EBCR) is set ...
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... LBA PCI LBA: 1710H PCI: NA Bit Default 31: 26:21 X 20:17 X 16:12 X 11: Note: Values programmed into this register vary with stepping. Refer to the Intel Processor Specification Update (272918) for the correct value. Datasheet Intel describes the fields of the two Device IDs ...
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... Intel i960 RX I/O Processor at 3.3 Volts DEVICE IDENTIFICATION ON RESET This page intentionally left blank. 76 Datasheet ...