GC80960RD66 Intel, GC80960RD66 Datasheet - Page 19

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Table 4.
Datasheet
Signal Descriptions (Sheet 2 of 4)
RST_MODE#
BE3:0#
DT/R#
Name
DEN#
D/C#/
Type
R(H)
P(Q)
P(Q)
H(Z)
H(Z)
H(Z)
R(0)
H(Z)
R(1)
P(1)
P(1)
I/O
O
O
O
BYTE ENABLES select which of up to four data bytes on the bus participate
in the current bus access. Byte enable encoding depends on the bus width
of the memory region accessed:
32-bit bus:
16-bit bus:
transactions, these signals do not toggle during a burst (32-bit bus only) from
the Intel
They remain active through the last T
DATA ENABLE indicates data transfer cycles during a bus access. DEN# is
asserted at the start of the first data cycle in a bus access and deasserted at
the end of the last data cycle. DEN# is used with DT/R# to provide control for
data transceivers connected to the data bus. DEN# has a weak internal
pullup which is active during reset to ensure normal operation when the
signal is not connected.
0 = Data Cycle
1 = Not a Data Cycle
DATA/CODE/RESET_MODE indicates that a bus access is a data access or
an instruction access. D/C# has the same timing as W/R#.
0 = Instruction Access
1 = Data Access
The RST_MODE# signal is sampled at Primary PCI bus reset to determine
whether the 80960 core is to be held in reset. When RST_MODE# is high,
the 80960RX begins initialization immediately following the deassertion of
P_RST. When RST_MODE is low, the 80960 core remains in reset until the
80960 core reset bit is cleared in the extended bridge control register. This
signal has a weak internal pullup that is active during reset to ensure normal
operation when the signal is left unconnected.
0 = RST_MODE enabled
1 = RST_MODE not enabled
While the 80960 core is in reset, all peripherals may be accessed from the
primary or secondary PCI buses depending on the status of the
WIDTH/HLTD1/RETRY/ signal.
DATA TRANSMIT / RECEIVE indicates the direction of data transfer to and
from the address/data bus. It is low during T
is high during
when DEN# is asserted.
0 = Receive
1 = Transmit
8-bit bus:
The processor asserts byte enables, byte high enable and byte low enable
during
BE3# enables data on AD31:24
BE2# enables data on AD23:16
BE1# enables data on AD15:8
BE0# enables data on AD7:0
BE3# becomes Byte High Enable (enables data on AD15:8)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
(increments with the assertion of LRDY# or RDYRCV#)
BE0# becomes Byte Low Enable (enables data on AD7:0)
BE3# is not used (state is high)
BE2# is not used (state is high)
BE1# becomes Address Bit 1 (A1)
(increments with the assertion of LRDY# or RDYRCV#)
BE0# becomes Address Bit 0 (A0)
(increments with the assertion of LRDY# or RDYRCV#)
T
a
®
. Since unaligned bus requests are split into separate bus
i960
®
T
a
core processor; they do toggle for DMA and ATU cycles.
and T
w
/T
Intel
d
cycles for a write. DT/R# never changes state
®
Description
i960
d
®
cycle.
RX I/O Processor at 3.3 Volts
a
and T
Package Information
w
/T
d
cycles for a read; it
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