GC80960RD66 Intel, GC80960RD66 Datasheet - Page 17

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

3.0
3.1
3.1.1
Table 3.
Datasheet
Package Information
Package Introduction
The 80960RX is offered in a SuperBGA* Ball Grid Array (HL-PBGA) package. This is a
perimeter array package with four rows of ball connections in the outer area of the
package. See
Section 3.1.1, “Functional Signal Definitions” on page 17
3.1.2, “352-Lead HL-PBGA Package” on page 30
Functional Signal Definitions
Table 3
defines signals associated with the bus interface.
basic control and test functions.
Table 7
DMA, APIC and I
Signal Type Definition
Symbol
S (...)
A (...)
R (...)
H (...)
P (...)
K (...)
OD
I/O
O
–
I
presents the legend for interpreting the Type Field in the following tables.
defines PCI signals.
Figure 4, “352L HL-PBGA Package Diagram (Bottom View)” on page
Input signal only.
Output signal only.
Signal can be either an input or output.
Open Drain signal.
Signal must be connected as described.
Synchronous. Inputs must meet setup and hold times relative to S_CLK.
S(E) Edge sensitive input
S(L) Level sensitive input
Asynchronous. Inputs may be asynchronous relative to S_CLK.
A(E) Edge sensitive input
A(L) Level sensitive input
While the P_RST# signal is asserted, the signal:
R(1) is driven to V
R(0) is driven to V
R(Q) is a valid output
R(Z) Floats
R(H) is pulled up to V
R(X) is driven to an unknown state
While the 80960RX is in the hold state, the signal:
H(1) is driven to V
H(0) is driven to V
H(Q) Maintains previous state or continues to be a valid outputH(Z) Floats
While the 80960RX is halted, the signal:
P(1) is driven to V
P(0) is driven to V
P(Q) Maintains previous state or continues to be a valid output
While the Secondary PCI Bus is being parked, the signal:
K(Z) Floats
K(Q) Maintains previous state or continues to be a valid output
2
C signals.
Table 8
Table 10
CC
SS
CC
SS
CC
SS
Table 6
CC
defines Memory Controller signals.
defines clock signals.
defines signals associated with the Interrupt Unit.
Intel
Description
Table 5
defines the signal and ball locations.
®
i960
describes signal function;
defines signals associated with
®
RX I/O Processor at 3.3 Volts
Table 11
Package Information
defines ICE signals.
Table 9
defines
Table 4
Section
31.
17